Semiconductor Interconnection Fabrication via Segmented Damascene Process
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Solution Overview
Problem
As semiconductor devices are scaled down, the aspect ratio of interconnections such as bit lines and word lines increases, making it difficult to reliably form these connections due to the challenge of achieving precise and reliable fabrication methods for high aspect ratio structures with low resistance.
Innovation Solution
A method of fabricating semiconductor devices involving the formation of sequentially stacked lower and upper conductive patterns, where the lower conductive patterns are formed using a photolithography and etch process, and the upper conductive patterns are formed using a damascene process, allowing for the creation of interconnection structures with high aspect ratios and low resistance, without the need for additional photolithography steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the line width of interconnections is scaled down to increase integration, then the aspect ratio becomes greater, but the reliability of forming interconnections deteriorates
Solution Approach 1:
The interconnection structure is divided into multiple segments: lower conductive patterns, upper conductive patterns, and insulating patterns between them. This segmentation allows each part to be optimized independently, with the lower conductive patterns providing structural support and the upper conductive patterns providing low-resistance electrical connection, thereby resolving the contradiction between scaling down and maintaining reliability.
Solution Approach 2:
Different regions of the interconnection structure are assigned different materials and properties: the lower conductive patterns use materials suitable for high aspect ratio formation, while the upper conductive patterns use low-resistance materials for optimal electrical performance. This local differentiation allows the structure to simultaneously achieve high aspect ratio stability and low resistance.
2Manufacturing precision
If photolithography and etch process is used to form lower conductive patterns, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The lower conductive patterns are formed first using photolithography and etch processes to establish precise high aspect ratio structures. These pre-formed patterns then serve as templates and alignment references for subsequent damascene processing of the upper conductive patterns, eliminating the need for additional photolithography steps and reducing overall process complexity.
3Reliability
If damascene process is used to form upper conductive patterns, then resistance is reduced, but manufacturing complexity increases
Solution Approach 1:
The formation of upper conductive patterns is merged with the planarization process. During chemical mechanical polishing (CMP) of the interlayer insulating layer, the sacrificial mask patterns are selectively removed to create openings, and the upper conductive material is simultaneously deposited and planarized in a single integrated process sequence, reducing manufacturing steps while achieving low resistance.
4Quantity of substance
If high aspect ratio interconnections are formed, then integration density is improved, but parasitic capacitance increases
Solution Approach 1:
Insulating patterns are introduced as intermediary elements between the lower conductive patterns and upper conductive patterns. These insulating layers electrically isolate the conductive elements while maintaining their close proximity for signal transmission, thereby reducing parasitic capacitance between adjacent interconnections while preserving high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of interconnection structures with high aspect ratios and low resistance, improving signal transmission speed and reducing parasitic capacitance, thereby enhancing the performance and reliability of semiconductor devices.
Implementation Method 1
The exposed sacrificial mask patterns may then be removed to form openings exposing the lower conductive patterns. The wet or vapor HF etching process may be used to remove the sacrificial mask patterns.
Implementation Method 2
forming interlayer insulating patterns by planarizing the interlayer insulating layer until the sacrificial mask patterns are exposed
Data Source
AI summary
A method of fabricating a semiconductor device includes forming switching devices on a substrate. A lower structure is formed in the substrate having the switching devices. A lower conductive layer is formed on the lower structure. Sacrificial mask patterns are formed on the lower conductive layer. Lower conductive patterns are formed by etching the lower conductive layer using the sacrificial mask patterns as an etch mask. An interlayer insulating layer is formed on the substrate having the lower conductive patterns. Interlayer insulating patterns are formed by planarizing the interlayer insulating layer until the sacrificial mask patterns are exposed. Openings exposing the lower conductive patterns are formed by removing the exposed sacrificial mask patterns. Upper conductive patterns self-aligned with the lower conductive patterns are formed in the openings.