Semiconductor Interconnection Structure Trench Depth Control
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Solution Overview
Problem
The formation of smaller through holes in semiconductor devices for increased metal layers is challenging, leading to degradation of electrical performance due to difficulties in forming high-quality interconnections, which can affect the normal operation of semiconductor devices.
Innovation Solution
A method involving a base substrate with distinct trench depths in different regions, where a first trench with a smaller depth is formed in the peripheral region and a second trench with a greater depth in the device region, allowing for controlled etching and formation of interconnection structures using conductive materials to connect base interconnection structures, thereby minimizing damage and enhancing electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of metal layers is increased to achieve ultra-large-scale integration, then the interconnection capability is improved, but the through hole size decreases and formation difficulty increases
Solution Approach 1:
The patent divides the through hole formation process into two distinct stages: first forming a shallow trench in the peripheral region, then forming a deeper trench in the device region. This segmentation allows each region to be optimized independently, resolving the contradiction between increased interconnection layers and through hole formation difficulty.
Solution Approach 2:
The patent applies different trench depths to different regions: a first depth for the peripheral region and a second (greater) depth for the device region. This local differentiation enables optimized etching control in each region, addressing the formation difficulty while maintaining interconnection capability.
2Ease of manufacture
If conventional through hole formation methods are used, then the process is simple, but the electrical performance degrades due to etching damage
Solution Approach 1:
The patent segments the etching process into region-specific operations with different depths and parameters. By controlling the etching depth differently in peripheral versus device regions, the method reduces etching damage to the base interconnection structure while maintaining process feasibility.
Solution Approach 2:
The patent changes the etching parameters (depth, duration, intensity) based on the specific region being processed. The device region receives more controlled, deeper etching while the peripheral region receives shallower etching, minimizing damage to underlying structures and improving electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the formation quality of through holes and interconnection structures, reducing the risk of etching damage to the base interconnection structures, thus enhancing the electrical performance and reliability of semiconductor devices.
Implementation Method 1
forming a first opening exposing the base interconnection structure in the medium layer in the device region and forming a second opening exposing the base interconnection structure in the medium layer in the peripheral region by etching the medium layer
Data Source
AI summary
A semiconductor structure is provided and includes a base substrate including a device region and a peripheral region surrounding the device region, the base substrate including a base interconnection structure formed in each of the device region and the peripheral region; a medium layer on the base substrate; a first interconnection structure through the medium layer and on the base interconnection structure in the device region; and a second interconnection structure through the medium layer and on the base interconnection structure in the peripheral region. The first interconnection structure includes: a first portion over the base interconnection structure, and a second portion partially on the first portion and partially on a portion of the medium layer.