Semiconductor Interconnection Layers with Variable Widths
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Solution Overview
Problem
Current semiconductor manufacturing methods face challenges in microfabricating devices with interconnection layers of different widths due to alignment margin requirements and resolution limits of exposure techniques, making it difficult to produce narrow and wide interconnections simultaneously.
Innovation Solution
The semiconductor device features a plurality of first interconnection layers with widths smaller than the exposure technique's resolution limit, with second and third interconnection layers of larger widths strategically placed between them, allowing for equal spacing that aligns with the first interconnection layers' spacing, and a manufacturing method involving mask layers, etching, and chemical mechanical polishing to achieve these configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If narrow interconnections and wide interconnections are formed in different lithography processes, then alignment margin is ensured, but the space between interconnections increases and device area expands
Solution Approach 1:
The patent combines the formation of narrow and wide interconnections into a single lithography process by using a common mask pattern. The mask is designed such that the same exposure conditions can form both narrow lines (where no mandrel is present) and wide lines (where mandrels are present), thereby ensuring alignment precision while reducing device area.
Solution Approach 2:
The patent introduces mandrels as intermediary structures that are selectively removed in specific regions. These mandrels act as placeholders during the lithography process, enabling the formation of wide interconnections while maintaining the same mask pattern used for narrow interconnections. The mandrels are subsequently removed to create the desired wide line spaces.
2Manufacturing precision
If interconnection layers of different widths are formed using conventional methods, then alignment margin is ensured, but the number of manufacturing steps increases
Solution Approach 1:
The patent merges multiple lithography processes into a single process by designing a unified mask pattern that can simultaneously define both narrow and wide interconnection regions. This eliminates the need for separate lithography steps, thereby maintaining alignment precision while improving manufacturing efficiency.
Solution Approach 2:
The patent performs preliminary actions by forming mandrel structures and insulation layers before the final interconnection formation. These preliminary structures are strategically placed and then selectively removed to create the desired wide interconnection regions, streamlining the manufacturing process.
3Manufacturing precision
If the space between narrow and wide interconnections is increased, then alignment margin is ensured, but the pitch between interconnections increases
Solution Approach 1:
The patent applies local quality by using the same mask pattern globally but creating local variations in interconnection width through the selective presence or absence of mandrels. This allows narrow interconnections to have sufficient spacing for alignment while wide interconnections can be formed in specific locations without increasing the overall pitch.
Solution Approach 2:
Mandrels serve as local intermediaries that are introduced only where wide interconnections are needed. By selectively placing and removing mandrels, the patent achieves variable interconnection widths without requiring increased spacing throughout the entire device, thereby maintaining small pitch while ensuring alignment margin where needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the simultaneous formation of interconnection layers with different widths in a single lithography process, reducing the number of manufacturing steps and ensuring precise alignment, thereby microfabricating semiconductor devices with reduced area and improved precision.
Implementation Method 1
reducing a width of each of the first mask layers and the second mask layer by selectively etching the first mask layers and the second mask layer
Implementation Method 2
forming a plurality of sidewalls on side surfaces of the first mask layers and the second mask layer
Implementation Method 3
selectively etching the insulating layer using the sidewalls as a mask to form, in the insulating layer, a plurality of first trenches and a second trench
Implementation Method 4
burying a conductor in the first trenches and the second trench to form, in the insulating layer, a plurality of first interconnection layers and a second interconnection layer
Implementation Method 5
the unnecessary interconnection material is removed by, e.g., chemical mechanical polishing (CMP)
Data Source
AI summary
A semiconductor device includes a plurality of first interconnection layers which are provided in an insulating layer and formed in a pattern having a width and space smaller than a resolution limit of an exposure technique, and a second interconnection layer which is provided between the first interconnection layers in the insulating layer and has a width larger than that of a first interconnection layer. A space between the second interconnection layer and each of first interconnection layers adjacent to both sides of the second interconnection layer equals the space between the first interconnection layers.