Semiconductor Interconnection Structure Using Via-First Capping Layer
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Solution Overview
Problem
The increasing complexity and miniaturization of semiconductor devices pose challenges in forming reliable semiconductor devices at smaller sizes, as the scaling-down process complicates fabrication and increases the difficulty of achieving reliable interconnections and reducing RC delay times.
Innovation Solution
The use of a low-k dielectric material and a via-first process with a capping layer to form conductive vias and interconnection structures, where the conductive vias are formed using lithography patterning before the deposition of the dielectric layer, reducing voids and damage, and ensuring low capacitance and improved reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If geometric size is decreased through scaling-down process, then functional density increases, but fabrication complexity increases and manufacturing difficulty increases
Solution Approach 1:
The patent applies preliminary action by forming the conductive via and placing the etch stop layer before depositing the low-k dielectric material. This sequence prevents damage to the dielectric layer during via formation and eliminates the need for complex post-deposition via creation processes, thereby reducing fabrication complexity while maintaining high functional density
Solution Approach 2:
The patent segments the interconnection structure into distinct functional layers: conductive via, etch stop layer, and low-k dielectric layer. This segmentation allows each layer to be optimized independently for its specific function, simplifying the overall fabrication process while achieving high functional density through precise control of each segment
2Productivity
If feature size continues to decrease, then IC production efficiency increases, but fabrication process difficulty increases
Solution Approach 1:
The conductive via is formed preliminarily before dielectric deposition, which simplifies the fabrication process at smaller feature sizes. This approach avoids the complexity of forming vias through already-deposited thin dielectric layers, making the process more manufacturable while maintaining high production efficiency
Solution Approach 2:
The etch stop layer acts as an intermediary between the conductive via and the low-k dielectric layer. It protects the dielectric layer from damage during via formation and provides a stable interface, thereby reducing fabrication process difficulty while enabling continued scaling for high productivity
3Reliability
If conventional via formation process is used after dielectric deposition, then interconnection structures can be formed, but voids and damage occur in the dielectric layer
Solution Approach 1:
The conductive via is formed before dielectric deposition, which eliminates the mechanical damage and voids that occur when vias are formed through already-deposited dielectric layers. This preliminary via formation ensures both high interconnection reliability and perfect dielectric layer integrity
Solution Approach 2:
The etch stop layer is placed beforehand to cushion and protect the low-k dielectric layer from any potential damage during subsequent processing steps. This protective layer ensures dielectric integrity while enabling reliable interconnection formation
4Speed
If standard dielectric material is used, then interconnection structures can be formed, but RC delay times increase and operation speed decreases
Solution Approach 1:
The patent changes the dielectric parameter by using low-k dielectric material with lower dielectric constant than standard materials. This parameter change reduces capacitance between interconnection lines, thereby reducing RC delay times and increasing operation speed while maintaining signal transmission reliability through the protective etch stop layer
Data Source
AI summary
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first conductive feature in a first dielectric layer and a second conductive feature over the first dielectric layer. The semiconductor device structure also includes a conductive via between the first conductive feature and the second conductive feature. The conductive via includes an etching stop layer over the first conductive feature, a conductive pillar over the etching stop layer, and a capping layer surrounding the conductive pillar and the etching stop layer. The first conductive feature and the second conductive feature are electrically connected to each other through the capping layer, the conductive pillar, and the etching stop layer. The semiconductor device structure further includes a second dielectric layer over the first dielectric layer and below the second conductive feature. The second dielectric layer surrounds the conductive via.