Semiconductor Interconnections with High Young's Modulus
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Solution Overview
Problem
Conventional semiconductor devices experience electrical shorting due to thermal expansion and contraction of solder layers, which cause high stress on protective films and interconnections, leading to potential contact between electric conductors.
Innovation Solution
The semiconductor devices incorporate electric conductors with a Young's modulus of 300 GPa or more, an embedded body to fill the space between conductors, inclined portions on the conductors, a configuration where the upper surface of one conductor is lower than the other, or conductors thinner than the solder layer to mitigate stress and prevent contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a solder layer is formed to cover the protective film, then the electrode is protected and electrical connection is achieved, but repeated thermal expansion and contraction causes high stress on the protective film and interconnection
Solution Approach 1:
The patent changes the physical parameter of the interconnection by forming it with a specific Young's modulus (300 GPa or more) to resist stress. This parameter change allows the interconnection to maintain its position despite thermal expansion and contraction of the solder layer, preventing sliding and electrical shorting while maintaining reliable electrical connection
2Reliability
If the interconnection is disposed at a distance from the electrode, then electrical shorting is prevented under normal conditions, but stress causes the interconnection to slide into contact with the electrode
Solution Approach 1:
The patent changes the mechanical parameter of the interconnection by selecting materials with high Young's modulus (300 GPa or more), making the interconnection rigid and resistant to stress-induced sliding. This ensures the interconnection maintains its positioned distance from the electrode even under thermal stress, preventing electrical shorting while maintaining position stability
3Strength
If the interconnection is made with higher Young's modulus, then resistance to stress-induced sliding is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies parameter change by specifying a minimum Young's modulus (300 GPa) for the interconnection material rather than using conventional softer materials. This clear quantitative specification simplifies the manufacturing process by providing explicit material selection criteria, making it easier to control quality and consistency while achieving the required stress resistance
Solution Approach 2:
The patent employs composite material structures, such as forming the interconnection as a multi-layer structure or using composite materials that achieve high Young's modulus while remaining compatible with existing semiconductor manufacturing processes. This approach maintains manufacturing feasibility while achieving the required mechanical strength
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These designs effectively suppress sliding and contact between electric conductors, preventing electrical shorting by relaxing stress and maintaining distance between interconnections and electrodes.
Implementation Method 1
A solder layer has a higher coefficient of thermal expansion than that of a protective film. Thus, in the semiconductor device, repeated expansion and contraction of the solder layer causes high stress to act on the protective film.
Implementation Method 2
The first electric conductor and the second electric conductor each have a Young's modulus of 300 GPa or more
Data Source
AI summary
A gate electrode is formed in a trench formed in a semiconductor substrate. A gate interlayer insulating film is formed to cover the gate electrode and the like. A gate interconnection and an emitter electrode are formed in contact with the gate interlayer insulating film. A glass coating film and a polyimide film are formed to cover the gate interconnection and the emitter electrode. A solder layer is formed to cover the polyimide film. The gate interconnection and the emitter electrode are each formed of a tungsten film, for example.