Semiconductor Interface Verification via Shifted Data Strobe Signals
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Solution Overview
Problem
Current semiconductor systems face challenges in verifying the normality or abnormality of interfaces during testing, particularly in chip-on-chip packages, where data transmission through micro-bump pads at high frequencies is complex, and existing test methods are not efficient in validating data windows and interface operations.
Innovation Solution
A semiconductor system comprising a first and second semiconductor device with data input/output units and a connector, capable of generating and shifting data strobe signals to store and verify internal data in test mode, allowing for electrical coupling and validation of data transmission between cell blocks, thereby enabling the verification of interface normality/abnormality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data transmission through micro-bump pads is performed at high frequency in chip-on-chip packages, then data transmission speed is improved, but interface verification complexity increases
Solution Approach 1:
The interface verification function is segmented into separate test modes (first test mode for data window verification, second test mode for interface normality verification). Each test mode uses dedicated data input/output units and connector configurations, allowing complex high-frequency interface verification to be broken down into manageable, isolated test operations that can be performed systematically.
Solution Approach 2:
The patent implements preliminary verification of data windows and interface conditions before actual high-frequency data transmission testing. By first verifying data integrity and window validity in controlled test modes, the system prepares and validates interface parameters in advance, making subsequent high-speed transmission verification more manageable and systematic.
2Productivity
If existing test methods are used for chip-on-chip packages, then test operations can be performed, but verification of data windows and interface operations is inefficient
Solution Approach 1:
The patent introduces intermediary data input/output units and connector components that facilitate controlled data transmission during testing. These intermediary elements act as mediators between test equipment and the actual high-frequency interface, enabling precise control and verification of data windows and interface operations without directly exposing the complex high-frequency path to simple test methods.
Solution Approach 2:
The system changes test parameters by operating in different test modes with different data strobe signal phases. By varying the phase of data strobe signals and configuring data input/output units differently in first and second test modes, the system can verify different aspects of interface performance, improving both the precision of verification and overall test efficiency.
3Reliability
If phase of data strobe signals is controlled during test mode, then interface normality can be verified, but test mode configuration complexity increases
Solution Approach 1:
The patent implements dynamic test mode configuration where the phase of data strobe signals can be adjusted and controlled during different test operations. The system dynamically switches between first and second test modes, dynamically configures data input/output units, and dynamically adjusts signal phases to verify different interface conditions, making the verification process adaptable and comprehensive without requiring overly complex fixed configurations.
Data Source
AI summary
A semiconductor device includes a first data input/output unit storing first internal input data in a first cell block in response to a first shift data strobe signal generated by shifting a first data strobe signal in a test mode, a second data input/output unit storing second internal input data in a second cell block in response to a second shift data strobe signal generated by shifting a second data strobe signal in the test mode, and a connector electrically coupling the first data input/output unit to the second data input/output unit in the test mode.