Semiconductor Interface Structure for Leakage Current Reduction
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Solution Overview
Problem
Vertical-type semiconductor devices face challenges in reducing channel resistance and controlling gate length and source/drain positions, leading to increased power consumption and leakage current, which hinders further integration and cost reduction in electronic apparatuses.
Innovation Solution
A semiconductor device with interface structures in the source/drain layers having different conduction or valence band energy levels, combined with a gate stack formed by epitaxial growth surrounding the channel layer, allows for reduced leakage current and improved performance by controlling gate length and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a polycrystalline channel material is applied in vertical-type devices, then the fabrication process is simplified, but the channel resistance is greatly increased making it difficult to stack multiple devices
Solution Approach 1:
The patent employs a composite channel structure consisting of a silicon germanium (SiGe) sacrificial layer combined with silicon nitride (SiN) spacer material. This composite approach allows the channel to achieve both low resistance through controlled doping and precise dimensional control through the spacer, resolving the contradiction between fabrication simplicity and electrical performance.
Solution Approach 2:
The silicon nitride spacer acts as an intermediary element that indirectly defines the gate length and channel dimensions. Rather than directly forming the channel, the spacer mediates the relationship between the deposited layers and the final active channel region, enabling precise control without complex lithography while maintaining good electrical characteristics.
2Reliability
If a single crystalline channel material is applied in vertical-type devices, then the channel resistance is reduced, but the gate length and relative positions of gate and source/drain are difficult to control
Solution Approach 1:
The silicon nitride spacer serves as a mediator that transfers the dimensional control function from lithography to a deposition-based process. The spacer's thickness, controlled by atomic layer deposition (ALD), precisely defines the gate length and source/drain positioning, achieving high manufacturing precision while maintaining process simplicity.
Solution Approach 2:
The patent replaces traditional mechanical/lithographic dimensioning methods with a deposition-based dimensional control system. Instead of relying on photolithography resolution to define gate length, the invention uses controlled thin film deposition thickness to precisely set dimensions, substituting a more controllable physical process for the limiting lithographic approach.
3Productivity
If conventional vertical-type device structures are used, then device stacking is enabled, but power consumption and leakage current increase hindering further integration
Solution Approach 1:
The patent systematically changes multiple parameters including channel width, doping concentration, and spacer thickness to optimize the balance between stacking capability and power consumption. By adjusting these parameters, the device achieves low leakage current through precise dimensional control while maintaining the vertical stacking architecture for high integration density.
Solution Approach 2:
The invention applies different properties to different regions: the channel region has precise dimensional control with optimized doping for low resistance, while the spacer regions provide electrical isolation to reduce leakage. This local differentiation of properties allows simultaneous achievement of low power consumption and stacking capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces leakage current and improves the performance of semiconductor devices by creating a built-in electric field and optimizing switching performance, while allowing for precise control of gate length and reducing parasitic capacitance.
Implementation Method 1
at least one interface structure is formed in at least one of the first source/drain layer and the second source/drain layer, the conduction band energy levels at both sides of the interface structure are different and/or the valence band energy levels at both sides of the interface structure are different
Implementation Method 2
a gate stack formed by epitaxial growth is provided in the semiconductor device, the gate stack surrounding the outer circumference of the channel layer
Data Source
AI summary
A semiconductor device, including: a substrate; a first source/drain layer, a channel layer, and a second source/drain layer sequentially stacked on the substrate and adjacent to each other, and a gate stack formed around an outer circumference of the channel layer; wherein at least one interface structure is formed in at least one of the first source/drain layer and the second source/drain layer, the conduction band energy levels at both sides of the interface structure are different and/or the valence band energy levels are different.