Semiconductor Device With Interlaced Trenches For Epitaxy Defect Control
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Solution Overview
Problem
Aspect ratio trapping (ART) technology faces challenges in controlling defects during epitaxy in semiconductor manufacturing, particularly when epitaxy is performed at later stages, where long direction defects in trenches are hard to manage, and at earlier stages, where epitaxy growth on flat silicon surfaces is difficult to control.
Innovation Solution
A semiconductor device fabrication method involving the deposition of dielectric and semiconductor layers with interlaced trenches, where the first semiconductor layer is grown within the first trenches and the second semiconductor layer is grown within the second trenches, both formed in dielectric layers, with CMP processes for planarization, to minimize lattice mismatch and defect formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If epitaxy is performed at the later process of manufacturing, then the trenches are well-formed with good aspect ratio, but long direction defects along trenches are hard to control
Solution Approach 1:
The patent divides the epitaxy process into two separate stages: first forming semiconductor layers in trenches (utilizing aspect ratio trapping), then performing additional epitaxy on the planarized surface. This segmentation allows each stage to optimize for its specific function - the first stage creates well-defined trenches with good aspect ratio, while the second stage enables defect control through surface planarization before epitaxy growth.
2Manufacturing precision
If epitaxy is performed at the former process of manufacturing, then the epitaxy grows on flat silicon surface, but it is hard to control epitaxy defects
Solution Approach 1:
The patent performs preliminary trench formation and semiconductor layer deposition before the final epitaxy growth. By first creating the trench structure and filling it with semiconductor material, then planarizing the surface, the patent establishes a controlled foundation that enables subsequent epitaxy to proceed with better defect control while maintaining proper trench geometry.
Solution Approach 2:
The patent transitions from three-dimensional trench formation to a two-dimensional planar surface for epitaxy growth. By filling trenches and planarizing the surface, the patent creates a flat growth substrate that eliminates the geometric constraints of trenches during epitaxy, thereby improving defect control while maintaining the underlying trench structure through the planarized surface.
3Manufacturing precision
If multiple semiconductor layers are formed in interlaced trenches, then lattice mismatch is reduced, but process complexity increases
Solution Approach 1:
The patent combines multiple semiconductor layers with different materials (e.g., SiGe and Si) into an integrated structure formed through coordinated epitaxy processes. By depositing dielectric layers, forming interlaced trenches, and performing sequential epitaxy operations, the patent merges multiple functions - lattice mismatch management, trench formation, and layer integration - into a unified process flow that achieves precise lattice control despite the increased number of steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces misfit defects and improves control over epitaxy growth by aligning the semiconductor layers' material composition and trench patterns, enhancing the overall quality and yield of semiconductor devices.
Implementation Method 1
A first semiconductor layer is grown on the first dielectric layer within the at least one first trench. A second semiconductor layer is grown on the second dielectric layer within the at least one second trench
Data Source
AI summary
A semiconductor device includes a substrate, a first dielectric layer, a first semiconductor layer, a second dielectric layer and a second semiconductor layer. The first dielectric layer is disposed on the substrate and includes at least one first trench formed in the first dielectric layer. The first semiconductor layer is disposed on the first dielectric layer and within the at least one first trench. The second dielectric layer is disposed on the first semiconductor layer and includes at least one second trench formed in the second dielectric layer, wherein in a planar view, the at least one first trench and the at least one second trench are not overlapped with each other. The second semiconductor layer is disposed on the second dielectric layer and within the at least one second trench.