Semiconductor Package Interlayer Design for Delamination Prevention
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Solution Overview
Problem
In semiconductor packages with side-by-side electronic components of varying thicknesses, existing technologies face challenges in enhancing adhesion among components, leading to issues like delamination and cracks due to differences in thermal expansion coefficients and modulus of materials used in interlayers and encapsulants.
Innovation Solution
A semiconductor package structure is designed with an interlayer that does not contact the lateral surfaces of electronic components, instead being limited to the upper surfaces and edges, using a non-conductive adhesive material with specific thermal expansion characteristics to improve adhesion and prevent delamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If an interlayer is used to attach electronic components, then adhesion among components is improved, but delamination and cracks occur due to differences in thermal expansion coefficients and modulus of materials
Solution Approach 1:
The patent introduces an interlayer as an intermediary substance between the encapsulant and electronic components. This interlayer has specifically tailored thermal expansion coefficients and modulus values that are intermediate between the encapsulant and the components, acting as a buffer to reduce stress concentration and prevent delamination and cracks caused by thermal expansion mismatches.
Solution Approach 2:
The patent modifies the physical and chemical parameters of the interlayer material, specifically controlling its thermal expansion coefficient and modulus to fall within certain ranges. By adjusting these parameters, the interlayer can accommodate thermal expansion differences between the encapsulant and electronic components, thereby improving adhesion while preventing delamination and crack formation.
2Volume of moving object
If electronic components are stacked for miniaturization, then package size is reduced, but adhesion enhancement becomes more critical due to varying thicknesses of side-by-side components
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked configuration of electronic components. This vertical stacking reduces the horizontal footprint and package size while the interlayer provides enhanced adhesion to accommodate the varying thicknesses of components in the stack, solving both miniaturization and adhesion challenges.
Solution Approach 2:
The patent applies the interlayer with specific material properties (thermal expansion coefficient and modulus within certain ranges) locally at the interfaces between electronic components and encapsulant. This localized application of specially tailored material properties ensures enhanced adhesion precisely where needed, accommodating the varying thicknesses of stacked components without compromising the entire package structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the adhesion among electronic components, reduces delamination and crack formation, and maintains effective thermal management by using materials with tailored thermal expansion properties.
Implementation Method 1
differences in thermal expansion coefficients and modulus of materials used in interlayers and encapsulants
Data Source
AI summary
The present disclosure provides a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a substrate, a first electronic component, an interlayer, a third electronic component and an encapsulant. The first electronic component is disposed on the substrate. The first electronic component has an upper surface and a lateral surface and a first edge between the upper surface and the lateral surface. The interlayer is on the upper surface of the first electronic component. The third electronic component is attached to the upper surface of the first electronic component via the interlayer. The encapsulant encapsulates the first electronic component and the interlayer. The interlayer does not contact the lateral surface of the first electronic component.