Semiconductor Device Interlayer Dielectric Film Contact Hole Design
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Solution Overview
Problem
Conventional semiconductor devices face challenges in reducing the mesa width while maintaining low contact resistance and preventing short circuits between the emitter electrode and the gate conductive section.
Innovation Solution
The semiconductor device incorporates a specific structure with a gate trench section, a dummy trench section, and an interlayer dielectric film, where the interlayer dielectric film is provided above the gate trench section and dummy trench section, and a contact hole is formed to expose the mesa section, ensuring the contact hole's width is equal to or greater than the mesa section's width, and the interlayer dielectric film's thickness varies to prevent short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the mesa width is reduced to improve device integration, then the area occupied by mesa sections decreases, but the contact resistance increases and short circuits between emitter electrode and gate conductive section occur
Solution Approach 1:
An interlayer dielectric film is introduced as an intermediary structure between the emitter electrode and gate conductive section. This dielectric film prevents direct contact (short circuit) while allowing controlled electrical connection through contact holes, thus reducing contact resistance without increasing mesa width. The dielectric film acts as a mediator that enables both isolation and connection functions simultaneously.
Solution Approach 2:
The solution moves from a two-dimensional planar contact approach to a three-dimensional vertical contact structure. Contact holes are formed vertically through the interlayer dielectric film to establish electrical connection, allowing the mesa width to be reduced horizontally while maintaining vertical electrical connectivity. This dimensional transition enables compact lateral spacing without compromising contact quality.
2Reliability
If the interlayer dielectric film thickness is increased to prevent short circuits, then the insulation between emitter electrode and gate conductive section improves, but the contact hole formation becomes more difficult and contact resistance increases
Solution Approach 1:
The interlayer dielectric film is configured with non-uniform thickness, being thicker in regions requiring enhanced insulation and thinner in regions where contact holes are formed. This local quality variation allows the dielectric film to provide maximum insulation where needed while maintaining manufacturable thickness for contact hole formation, thus balancing insulation performance with fabrication feasibility.
Solution Approach 2:
Contact holes are formed through the interlayer dielectric film before final electrode deposition. This preliminary action of creating conductive pathways through the dielectric layer ensures that subsequent electrode materials can establish reliable electrical connection without requiring excessive dielectric thickness removal, thereby maintaining both insulation and contact quality.
3Reliability
If the contact hole width is increased to reduce contact resistance, then the electrical connection between emitter electrode and mesa section improves, but the precision of mesa section exposure decreases
Solution Approach 1:
The contact hole geometry transitions from a wide lateral opening to a controlled vertical cylindrical structure. By forming deep, narrow contact holes through the interlayer dielectric film, the design achieves low contact resistance through adequate hole width while maintaining precise lateral positioning that accurately exposes only the intended mesa section areas, thus balancing electrical connection with fabrication precision.
Data Source
AI summary
Provided is a semiconductor device comprising: a semiconductor substrate; a gate trench section that is provided from an upper surface to an inside of the semiconductor substrate and extends in a predetermined extending direction on the upper surface of the semiconductor substrate; a mesa section in contact to the gate trench section in an arrangement direction orthogonal the extending direction; and an interlayer dielectric film provided above the semiconductor substrate; wherein the interlayer dielectric film is provided above at least a part of the gate trench section in the arrangement direction; a contact hole through which the mesa section is exposed is provided to the interlayer dielectric film; and a width of the contact hole in the arrangement direction is equal to or greater than a width of the mesa section in the arrangement direction.