Semiconductor Interlayer Connection Hole Etching
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Solution Overview
Problem
In semiconductor devices with shared contact structures, excessive etching of shallow conductive material layers during the formation of connection holes leads to overetching, resulting in metal deposits on the side walls, reduced yield, and increased electrical resistance due to incomplete coverage by the final metal filling.
Innovation Solution
A semiconductor device and manufacturing method featuring a connection hole with a large-diameter and small-diameter concave portion, where the shallow conductive layer is exposed minimally by using a small-diameter resist pattern as a mask, preventing excessive etching and ensuring proper conductivity and connection between conductive layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a single resist pattern is used to etch the interlayer insulating film until both conductive layers are exposed, then a shared contact structure is formed with high-density integration, but the shallow conductive material layer is subjected to plasma for an extended period causing overetching
Solution Approach 1:
The patent divides the etching process into two separate steps using two different resist patterns. First, a first resist pattern is used to etch until the shallow conductive layer is exposed. Then, a second resist pattern is used to etch until the deep conductive layer is exposed. This segmentation prevents the shallow layer from being exposed to plasma for an extended period, thereby preventing overetching and metal deposit formation while still achieving the space-saving shared contact structure.
2Ease of manufacture
If the shallow conductive material layer is excessively etched, then the interlayer insulating film can be fully removed to expose both conductive layers, but metal deposits form on the side wall and electrical resistance increases
Solution Approach 1:
The patent performs a preliminary etching step using the first resist pattern to expose the shallow conductive layer before performing the main etching step. This preliminary action creates a stop condition that prevents excessive etching during the subsequent second etching step, ensuring that the shallow layer is not over-etched and metal deposits are prevented, thereby maintaining electrical connection reliability.
3Object-generated harmful factors
If chemical posttreatment is applied to remove metal deposits, then side wall cleanliness is improved, but the process complexity increases and yield is reduced
Solution Approach 1:
The patent converts the potential harm of extended plasma exposure into a benefit by using it deliberately to expose the shallow conductive layer in a controlled first etching step. By planning this exposure and stopping the etching at this point using the first resist pattern, the shallow layer serves as an etching stop marker, preventing overetching and metal deposit formation in the subsequent second etching step, thereby eliminating the need for chemical posttreatment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes excessive etching of the shallow conductive layer, enhancing the yield and conductivity of the semiconductor device by preventing metal deposits and ensuring proper connection between conductive layers, thus reducing electrical resistance.
Implementation Method 1
the shallow conductive material layer that is exposed earlier to be subjected to plasma for an extended period of time during etching of the interlayer insulating film
Data Source
AI summary
Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers.