Semiconductor Interlayer Insulating Films Young's Modulus Stress
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Solution Overview
Problem
The miniaturization of multilayer wiring in semiconductor chips leads to increased resistance and parasitic capacitance, causing signal delays and potential malfunction, especially when packaged with resin, where thermal expansion differences result in stress-induced exfoliation of low-dielectric-constant interlayer films, compromising device reliability.
Innovation Solution
A semiconductor device manufacturing method involving a multilayer wiring structure with interlayer insulating films of varying Young's modulus, where a high-Young's-modulus film is used as the contact interlayer insulating film, a middle-Young's-modulus film as the first interlayer insulating film, and a low-Young's-modulus film as the second interlayer insulating film, to distribute stress and prevent exfoliation, while maintaining low dielectric constant for reduced capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a low-dielectric-constant film is used as the interlayer insulating film to reduce parasitic capacitance, then signal delay is reduced, but the film exfoliates due to stress from thermal expansion differences with the resin package
Solution Approach 1:
The patent changes the physical parameter of Young's modulus of the interlayer insulating film from low to high. By selecting a film with high Young's modulus (≥30 GPa, preferably ≥40 GPa), the film gains sufficient mechanical strength to resist stress-induced exfoliation while maintaining its low dielectric constant property, thus resolving the contradiction between reducing signal delay and preventing film exfoliation
Solution Approach 2:
The patent employs a composite material approach by combining the low-dielectric-constant film with a planarization film having high Young's modulus. This composite structure allows the low-dielectric-constant film to provide low parasitic capacitance while the high-modulus planarization film provides mechanical support to prevent exfoliation under thermal stress
2Productivity
If the wiring is miniaturized to achieve high integration, then more wirings can be packed, but resistance increases and signal delay worsens
Solution Approach 1:
The patent changes the material parameter from aluminum to copper for the wiring. Copper has lower resistivity than aluminum, which compensates for the increased resistance caused by miniaturization. This allows higher integration density to be achieved without significant increase in signal delay
Solution Approach 2:
The patent applies different material properties to different parts of the wiring structure. By using copper specifically for the wiring layers where resistance is critical, while using low-dielectric-constant materials for the insulating layers where capacitance reduction is critical, the patent optimizes both resistance and capacitance characteristics simultaneously
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces signal delays and enhances the reliability of semiconductor devices by distributing stress across multiple interfaces, preventing exfoliation and maintaining performance without increasing parasitic capacitance.
Implementation Method 1
distributing stress across multiple interfaces, preventing exfoliation
Implementation Method 2
thermal expansion differences result in stress-induced exfoliation
Implementation Method 3
increase in parasitic capacitance due to a reduction in the distance between wirings have become apparent
Implementation Method 4
forming a part of the interlayer insulator provided between wirings with a low-dielectric-constant film having a low dielectric constant
Data Source
AI summary
A preferred aim of the invention is to provide technique for improving reliability of semiconductor devices when using a low-dielectric-constant film having a lower dielectric constant than a silicon oxide film to a part of an interlayer insulating film. More specifically, to achieve the preferred aim, an interlayer insulating film IL1 forming a first fine layer is formed of a middle-Young's-modulus film, and thus it is possible to separate an integrated high-Young's-modulus layer (a semiconductor substrate 1S and a contact interlayer insulating film CIL) and an interlayer insulating film (a low-Young's-modulus film; a low-dielectric-constant film) IL2 forming a second fine layer not to let them directly contact with each other, and stress can be diverged. As a result, film exfoliation of the interlayer insulating film IL2 formed of a low-Young's-modulus film can be prevented and thus reliability of semiconductor devices can be improved.