III-V Semiconductor Structure Using Intermetallic Contacts
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Solution Overview
Problem
Traditional III-V based high electron mobility transistors are costly to produce due to the use of expensive metal formation processes like gold evaporation, necessitating a method to manufacture these transistors using existing silicon fabrication tools.
Innovation Solution
A semiconductor structure is developed using a GaN high mobility transistor with a heterojunction between gallium nitride (GaN) and aluminum gallium nitride (AlGaN) layers, where intermetallic compounds like Al, Ti, or Cu replace gold in the source and drain features, and a conductive gate is formed using refractory metals, allowing for the use of silicon fabrication tools.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional III-V processes are used with gold evaporation and ohmic structures, then high electron mobility transistor performance is achieved, but production cost increases significantly
Solution Approach 1:
The patent replaces expensive gold materials with cheaper alternative materials for metal formation and ohmic structures. Specifically, it uses aluminum (Al), titanium (Ti), copper (Cu), and other non-gold materials to form contact structures, gates, and interconnects, thereby eliminating the need for costly gold evaporation processes while maintaining device functionality.
Solution Approach 2:
The patent enables existing silicon fabrication tools to be used for manufacturing III-V based transistors by adapting standard silicon process tools (such as CVD, PECVD, sputtering, and ion implantation equipment) to deposit and process alternative metal materials, thus eliminating the need for specialized gold evaporation equipment and reducing manufacturing complexity.
2Reliability
If gold is used in ohmic structures and metal formation, then reliable electrical contact is achieved, but gold contamination occurs and costs increase
Solution Approach 1:
The patent substitutes gold with alternative materials such as aluminum, titanium, copper, and tungsten for all metal formation steps including ohmic contacts, gates, and interconnect structures. This eliminates gold contamination entirely while maintaining electrical contact reliability through optimized material stacks and deposition processes.
Solution Approach 2:
The patent extracts and removes gold from the entire fabrication process by replacing it with non-gold materials. The process explicitly avoids any steps that would introduce gold, including gold evaporation, gold sputtering, or gold plating, thereby eliminating the harmful contamination effect while preserving device performance.
3Manufacturing precision
If specialized III-V fabrication tools are used, then high quality III-V transistors are produced, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent makes existing silicon fabrication tools multi-functional by enabling them to process III-V materials and deposit alternative metal materials. Standard silicon tools such as PECVD reactors, sputtering chambers, and ion implanters are used to deposit aluminum, titanium, copper, and other materials on III-V substrates, thereby eliminating the need for specialized equipment while maintaining manufacturing precision.
Solution Approach 2:
The patent adjusts process parameters of existing silicon fabrication tools to accommodate III-V material processing and alternative metal deposition. This includes modifying deposition temperatures, pressures, and rates, as well as adjusting ion implantation energies and doses, to achieve high-quality III-V transistor structures using standard silicon process equipment.
Data Source
AI summary
A semiconductor structure comprises a first layer. The first layer comprises a first III-V semiconductor material. The semiconductor structure also comprises a second layer over the first layer. The second layer comprises a second III-V semiconductor material different from the first III-V semiconductor material. The semiconductor structure further comprises an insulating layer over the second layer. The insulating layer is patterned to expose a portion of the first layer. The exposed portion of the first layer comprises electrons of the second layer. The semiconductor structure additionally comprises an intermetallic compound over the exposed portion of the first layer.