Semiconductor Chip Interposer with Dielectric Recesses for Dual-Surface Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge lies in effectively connecting semiconductor chips with contact elements on both main surfaces to electronic devices, particularly when these devices need to be securely fixed on electronic boards, as existing methods face issues with alignment and attachment of conductive members due to differing plane orientations of contact elements and connectors.
Innovation Solution
The solution involves using flexible layer structures with a polymer-based carrier layer, a conductive layer, and a dielectric layer, where conductive members are positioned in recesses of the dielectric layer and attached in a form-fitting manner to align with contact elements and connectors, allowing for secure electrical connections and potential removal of the carrier layer post-fabrication to enhance conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact elements are arranged on both main surfaces of the semiconductor chip, then electrical connectivity is improved, but alignment and attachment of conductive members becomes more difficult due to differing plane orientations
Solution Approach 1:
The patent transitions from planar arrangement to three-dimensional spatial arrangement by using recesses in the dielectric layer to accommodate conductive members. This allows conductive members to be positioned at different depths and orientations, enabling connection between contact elements on opposite surfaces of the semiconductor chip while maintaining proper alignment despite the differing plane orientations.
Solution Approach 2:
The dielectric layer with recesses acts as an intermediary structure between the conductive members and the semiconductor chip. The recesses provide a controlled interface that facilitates precise positioning and alignment of conductive members, solving the alignment difficulty caused by connecting contact elements on both surfaces of the chip.
2Ease of manufacture
If flexible layer structures with polymer-based carrier layers are used, then ease of attachment is improved, but additional processing steps are required to remove carrier layers and add conductive layers
Solution Approach 1:
The polymer-based carrier layer serves as a preliminary support structure that facilitates the attachment process. It provides a stable base for positioning and attaching conductive members before the final device structure is completed. The carrier layer is temporarily retained during fabrication and removed in a subsequent step, enabling easier initial attachment while accepting the additional processing step as a trade-off for manufacturing ease.
3Reliability
If additional conductive layers are added post-fabrication, then thermal and electrical resistance is reduced, but device complexity increases
Solution Approach 1:
Additional conductive layers are added locally at specific positions where thermal and electrical conductivity needs to be enhanced, rather than uniformly throughout the entire device. This targeted approach reduces resistance where needed while minimizing the overall increase in device complexity by limiting the additional layers to only the necessary locations.
Data Source
AI summary
An electronic device includes a semiconductor chip. A contact element, an electrical connector, and a dielectric layer are disposed on a first surface of a conductive layer facing the semiconductor chip. A first conductive member is disposed in a first recess of the dielectric layer. The first conductive member electrically connects the contact element of the semiconductor chip with the conductive layer. A second conductive member is disposed in a second recess of the dielectric layer. The second conductive member electrically connects the conductive layer with the electrical connector.