Semiconductor Interposer Structure for Fine-Pitch, Stress-Resistant Packaging
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Solution Overview
Problem
Current interposer technologies face challenges in providing high bandwidth communication channels and resistance to physical stress, particularly due to limitations in line spacing and thermal expansion mismatch between semiconductor die and organic interposers.
Innovation Solution
The development of semiconductor interposers with a silicon core and multiple redistribution structures on each side, incorporating vertical interconnects and circuit components to enhance performance and resistance to stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If organic interposers are used, then resistance to cracking and damage from physical or thermal stresses is improved, but line spacing capability deteriorates (cannot achieve less than 10/10μ LS)
Solution Approach 1:
The patent employs a composite structure combining an organic interposer core with a silicon layer formed on its surface. The organic core provides stress resistance and flexibility, while the silicon layer enables fine-line patterning with sub-10μm spacing. This composite approach allows the interposer to simultaneously achieve crack resistance from the organic material and high-precision line spacing from the silicon layer, resolving the contradiction between reliability and manufacturing precision.
2Strength
If organic interposers are used, then resilience against physical stress is improved, but coefficient of thermal expansion mismatch with semiconductor die worsens
Solution Approach 1:
The patent applies local quality by differentiating the material properties at different locations and interfaces. The organic interposer core provides resilience and stress absorption, while the silicon layer on the surface provides thermal expansion compatibility with semiconductor die. By localizing the material properties to match specific functional requirements at different interfaces, the patent resolves the contradiction between overall resilience and localized thermal stress compatibility.
3Ease of manufacture
If conventional organic interposer processes are used, then ease of manufacture is improved, but minimum contact spacing capability worsens (cannot match semiconductor die contact spacing)
Solution Approach 1:
The silicon layer acts as an intermediary between the organic interposer manufacturing process and the semiconductor die attachment requirements. The organic interposer can be manufactured using conventional flexible processes, and the silicon layer is then formed on its surface to provide the necessary sub-10μm line spacing and contact spacing. This intermediary layer enables the transition from low-precision organic processing to high-precision contact spacing without requiring complete process overhaul.
Data Source
AI summary
Described are semiconductor interposer, and microelectronic device assemblies incorporating such semiconductor interposers. The described interposers include multiple redistribution structures on each side of the core; each of which may include multiple individual redistribution layers. The interposers may optionally include circuit elements, such as passive and/or active circuit. The circuit elements may be formed at least partially within the semiconductor core.