Semiconductor Interposer Resistor Configuration for Signal Integrity

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Solution Overview

Problem

High-speed semiconductor devices face challenges in maintaining signal integrity due to signal distortion, which existing technologies have not adequately addressed, especially during performance evaluations.

Innovation Solution

A semiconductor device and package design that includes an interposer with specific resistor configurations to connect a tester to semiconductor chips, reducing signal distortion by matching resistance and improving signal integrity through parallel resistor connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If high-speed signal transmission is implemented between semiconductor chips, then operating speed is improved, but signal distortion increases and signal integrity deteriorates

Engineering Contradiction:
Improveoperating speedVSAvoidsignal integrity
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

An interposer is introduced as an intermediary component between the tester and the semiconductor device. The interposer includes a reference voltage terminal that provides a stable reference potential, and signal lines with controlled impedance that act as mediators to transmit signals while maintaining signal integrity. This intermediary structure isolates the high-speed signal path from disturbing elements, reducing signal distortion during high-speed operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements impedance matching by carefully controlling the electrical parameters of signal lines and resistor values. The signal lines are designed with specific impedance characteristics, and resistors are selected with precise resistance values to match impedance at interfaces. This parameter optimization minimizes signal reflections and distortions, enabling high-speed signal transmission while maintaining signal integrity.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If signal transmission monitoring is added to evaluate signal integrity, then measurement capability is improved, but device complexity increases

Engineering Contradiction:
Improvesignal measurement capabilityVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The interposer serves multiple functions simultaneously: it provides mechanical support, electrical connection, impedance matching, and reference voltage supply. By integrating these functions into a single component, the patent achieves signal monitoring capability without proportionally increasing device complexity. The same interposer structure that enables high-speed transmission also facilitates signal integrity evaluation.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The interposer acts as an intermediary that provides a controlled environment for signal monitoring. It includes dedicated reference voltage terminals and signal lines with known characteristics, allowing the tester to accurately measure signal integrity without the complexity of incorporating measurement circuits directly into the semiconductor device under test.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9966317B2Semiconductor device and semiconductor package comprising the same
Publication Date: 2018.05.08 SAMSUNG ELECTRONICS CO LTD
  • US9966317B2 patent drawing
  • US9966317B2 patent drawing
  • US9966317B2 patent drawing

AI summary

A semiconductor device may include a first terminal electrically connected to a first semiconductor chip, a second terminal electrically connected to a second semiconductor chip, which is different from the first semiconductor chip, a first signal line electrically connecting the first terminal and the second terminal and including a first node, a third terminal connected to a tester monitoring a signal transmitted between the first semiconductor chip and the second semiconductor chip, a fourth terminal applied a reference voltage, a second signal line electrically connecting the third terminal and the fourth terminal and including a second node, a first resistor connected between the first node and the second node and a second resistor directly connected to the second node different from the first resistor.