Semiconductor Package Interposer Thermal Management
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving sufficient space for mounting passive components and secure stacking due to metal pads and warpage issues, which hinder heat release and integration performance.
Innovation Solution
The solution involves a semiconductor package structure with a first substrate, a flip-chip mounted first chip, a molding, an interposer made of aluminum oxide, and a second substrate with conductive balls, allowing for efficient heat dissipation and integration by forming vias and using a wire bonding method for chip connection, along with additional passive components and conductive balls for enhanced connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal pads are formed around the chip to connect upper and lower layer packages, then electrical connection between packages is achieved, but the mounting area is reduced making it difficult to mount passive components
Solution Approach 1:
A carrier board is introduced as an intermediary component between the upper and lower layer packages. The carrier board includes a cavity that receives the lower layer package and provides mounting areas for passive components. Electrical connections are established through conductive structures on the carrier board rather than metal pads around the chip, thus preserving the chip's mounting area while achieving package-to-package connectivity.
2Productivity
If packages are stacked to achieve higher integration, then functional density is improved, but warpage occurs making secure stacking difficult
Solution Approach 1:
The carrier board is designed with specific structural parameters including a cavity configuration that accommodates the lower layer package and support structures that provide mechanical stability. The cavity walls and support structures are dimensioned to compensate for warpage effects, ensuring stable stacking. Additionally, the carrier board material and thickness are selected to minimize thermal expansion differences that cause warpage during the stacking process.
3Volume of moving object
If package size is reduced to achieve miniaturization, then device compactness is improved, but heat release performance deteriorates
Solution Approach 1:
Heat dissipation is addressed by utilizing the vertical dimension through the carrier board structure. The carrier board provides thermal pathways that extend vertically from the chip to the outer surfaces of the stacked package assembly. Thermal vias and heat sinks integrated into the carrier board structure enable efficient heat release in the vertical direction, compensating for the reduced horizontal surface area available for heat dissipation in miniaturized packages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves heat-releasing performance and enables higher integration by providing a secure stacking mechanism and sufficient space for passive components, addressing the limitations of existing technologies.
Implementation Method 1
an interposer, which is placed on the first molding, and on both sides of which a pre-designed pattern is formed respectively
Implementation Method 2
The first via may be a solder bump
Implementation Method 3
a second substrate, which is placed on the interposer with at least one conductive ball positioned in-between, such that the second substrate is electrically connected with the pattern formed on the interposer
Data Source
AI summary
A method of manufacturing a semiconductor package which includes mounting a first chip on a first substrate by a flip chip method, the first substrate having a pre-designed pattern formed thereon; forming at least one bump by performing soldering, on at least one predetermined position electrically connected with the pattern formed on the first substrate; forming a first molding by performing molding, such that the first molding covers the first substrate and the first chip; placing an interposer on the first molding; and placing a second substrate on the interposer, the second substrate having a second chip mounted thereon.