Semiconductor Interposer Through Electrode High Density
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Solution Overview
Problem
The existing semiconductor devices face limitations in the number of bonding wires that can be connected to a circuit forming surface and the density of interconnections, which restricts the functionality of semiconductor chips, especially when high power consumption circuits are involved, leading to space constraints for signal and power interconnections.
Innovation Solution
The semiconductor device employs a first interposer with a through electrode connecting the circuit forming surface to the back surface, allowing for high-density interconnections between a first chip and a second chip group, with the power supply voltage being provided through the through electrode, thereby freeing up space in the second interposer for other interconnections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If bonding wires are used to connect the semiconductor chip, then the chip can be electrically connected with other devices, but the number of bonding wires that can be connected to the circuit forming surface is limited, which restricts the functionality of the semiconductor chip
Solution Approach 1:
An interposer substrate is introduced as an intermediary component between the semiconductor chip and the external environment. The interposer substrate provides a platform with multiple connection terminals that can be connected to the chip's circuit forming surface, effectively replacing the bonding wire connection method and enabling a greater number of electrical connections without being constrained by the limitations of bonding wire capacity.
2Power
If the width of interconnection is increased to supply power to high power consumption circuits, then power supply capability is improved, but the space available for arranging signal interconnections is further limited in the interposer
Solution Approach 1:
The interposer substrate utilizes its planar surface area to arrange multiple interconnection paths in different spatial regions. Power interconnections can be positioned in areas where they do not conflict with signal interconnection routes, allowing both wide power supply paths and numerous signal connections to coexist on the same substrate without mutual interference, effectively resolving the space conflict through optimized spatial arrangement.
Data Source
AI summary
A semiconductor device includes a first interposer provided with a first chip first interconnection; a first chip arranged to contact the first interposer in one surface of the first chip; a second interposer arranged to contact the other surface of the first chip and provided with a first chip second interconnection; and a second chip group mounted on the second interposer. The first chip has a circuit forming surface on which a circuit element is formed, as one of the surfaces of the first chip, and the first chip first interconnection and the first chip second interconnection are electrically connected with the circuit element. A through electrode is formed to pass from the one of the surfaces of the first chip to the other surface, and one of the first chip first interconnection and the first chip second interconnection is electrically connected with the circuit element through the through electrode.