3D Stacked Semiconductor Device With Interposer Via Communication Paths
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Solution Overview
Problem
Semiconductor devices with multicore processors face inefficiencies in communication speed due to shared I/O regions and long communication distances between processor and memory chips, leading to performance degradation and increased costs.
Innovation Solution
A semiconductor device design featuring a first semiconductor chip with multiple functional blocks connected through communication paths that penetrate an interposer, allowing for parallel communication and reducing communication distance between chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a memory region is provided in a semiconductor chip including a processor core, then communication speed between processor core and memory region is improved, but area of the semiconductor chip increases
Solution Approach 1:
The patent transitions from a planar 2D layout to a 3D stacked architecture where the processor chip and memory chip are vertically arranged and connected via through-silicon vias. This dimensional change allows memory to be physically closer to the processor core without increasing the footprint area of the processor chip, thereby improving communication speed while maintaining compact form factor.
Solution Approach 2:
The patent implements a stacked configuration where the memory chip is positioned directly on top of the processor chip, creating a nested vertical arrangement. This nesting allows the memory region to be integrated in the third dimension (vertical stacking) rather than occupying additional horizontal area, thus improving communication speed without increasing chip area.
2Quantity of substance
If through-silicon via is formed in memory chip for communication, then large-capacity memory can be allocated to each processor core, but parasitic capacitance increases which disturbs communication speed
Solution Approach 1:
The patent extracts the problematic insulating layer from the sidewalls of the through-silicon vias, leaving only the conductive via structure. By removing the insulating material that was previously present on the sidewalls, the parasitic capacitance is reduced, thereby improving communication speed while maintaining the ability to allocate large-capacity memory through the vertical via connections.
3Productivity
If number of through-silicon vias is increased to increase communication paths, then communication capacity is improved, but cost of memory chip per unit capacity increases
Solution Approach 1:
The patent designs the memory chip structure with shared through-silicon vias that can serve multiple processor cores simultaneously. This multi-functional approach allows a single via to provide communication paths to multiple cores, increasing communication capacity without proportionally increasing the number of vias manufactured, thereby controlling production costs.
4Device complexity
If processor chip and memory chip are connected through long distance communication path in substrate, then device integration is achieved, but communication delay increases leading to performance degradation
Solution Approach 1:
The patent introduces an interposer as an intermediary substrate that facilitates direct vertical connections between the processor chip and memory chip through through-silicon vias. This interposer mediator enables short-distance high-speed communication paths, eliminating the need for long-distance signals through the system board while maintaining system integration.
Data Source
AI summary
A method of manufacturing a semiconductor device including a PMOS transistor and a NMOS transistor is described. The method facilitates obtaining a FUSI phase of a suitable composition for the NMOS transistor and the PMOS transistor respectively, with fewer mask layers and through a fewer number of manufacturing steps.