Semiconductor Interrupt Priority Circuit Failure Detection
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Solution Overview
Problem
Existing semiconductor devices require a long time to detect failures in priority determination circuits due to the need for software-based checking of interrupt request flags, especially in systems with multiple interrupt factors, leading to inefficiencies and potential delays in failure detection.
Innovation Solution
A semiconductor device configuration that includes multiple processor elements, priority determination circuits, a checker circuit, and a control circuit to quickly select and compare interrupt request signals, allowing for rapid failure detection without increasing hardware complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software-based checking of interrupt request flags is used, then failure detection can be performed, but detection time becomes excessively long especially with multiple interrupt factors
Solution Approach 1:
The patent replaces software-based checking with a hardware-based failure detection mechanism. A dedicated failure detection circuit continuously monitors interrupt request flags in hardware, eliminating the need for software to read and compare flags. This hardware substitution enables continuous, real-time monitoring without the time overhead of software processing, directly resolving the contradiction between maintaining detection capability and reducing detection time.
Solution Approach 2:
The patent implements preliminary action by continuously monitoring interrupt request flags in advance through the failure detection circuit. Instead of waiting for software to periodically check flags, the hardware circuit proactively and continuously tracks flag states, preparing failure detection information ready for immediate processing. This preliminary continuous monitoring eliminates detection delays that would occur with periodic software checking.
2Speed
If hardware-based failure detection is implemented, then detection speed improves, but hardware complexity and resource usage increase
Solution Approach 1:
The failure detection circuit is designed with multi-functionality to reduce overall hardware complexity. The same detection circuit can monitor multiple interrupt request flags from different interrupt sources and different CPU contexts. By making the detection circuit universal rather than dedicated to each specific flag or CPU, the patent achieves fast continuous monitoring without proportionally increasing hardware resources.
Solution Approach 2:
The patent merges the failure detection function with the existing interrupt control hardware structure. The detection circuit is integrated into the interrupt controller architecture, sharing resources and logic with the existing interrupt handling mechanisms. This merging approach enables fast hardware-based detection while avoiding the overhead of completely separate monitoring hardware, thus reducing overall device complexity.
Data Source
AI summary
The present invention relates to a semiconductor device having a first processor element configured to receive a first interrupt request signal, a second processor element configured to receive a second interrupt request signal, a first priority determination circuit configured to receive a plurality of interrupt signals and to output the first interrupt request signal to the first processor element, a second priority determination circuit configured to receive the plurality of interrupt signals and to output the second interrupt request signal to the second processor element, a checker circuit configured detect failures of the first priority determination circuit and the second priority determination circuit, and a control circuit configured to select one of the first priority determination circuit or the second priority determination circuit as a circuit to be checked. The control circuit selects the circuit to be checked based on the first interrupt request signal and the second interrupt request signal.