Semiconductor Interruption Buffer Memory Prioritization
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Solution Overview
Problem
Semiconductor devices face increased circuit scale and power consumption due to the need for a large interruption buffer memory to store all interruption subroutine programs, which hinders high interruption response performance.
Innovation Solution
Implementing a semiconductor device with an interruption buffer memory that stores only the top M interruption subroutine programs with high occurrence probabilities, determined by occurrence counters or expected value calculation circuits, allowing for efficient execution without constant flash memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an interruption buffer memory is provided to store all interruption subroutine programs, then interruption response performance is improved, but circuit scale is increased
Solution Approach 1:
The patent applies local quality by differentiating the storage characteristics of two types of programs in the interruption buffer memory: frequently occurring interruption programs are stored with high priority in readily accessible memory regions, while less frequent programs are stored in other regions. This selective storage strategy ensures that the most critical interruption responses can be executed quickly without requiring the entire buffer to be optimized for maximum speed, thus improving interruption response performance while controlling circuit scale.
Solution Approach 2:
The patent implements partial action by storing only the most frequently occurring interruption programs in the interruption buffer memory, rather than all possible interruption programs. The determination circuit identifies and prioritizes these frequent programs based on occurrence frequency or importance, loading them into the buffer in advance. This partial pre-loading approach provides sufficiently high interruption response performance for common cases while avoiding the need to allocate memory space for every possible interruption scenario, thereby controlling circuit scale.
2Reliability
If an interruption buffer memory is provided to store all interruption subroutine programs, then interruption response performance is improved, but power consumption is increased
Solution Approach 1:
The patent applies local quality by differentiating the storage characteristics of two types of programs in the interruption buffer memory: frequently occurring interruption programs are stored with high priority in readily accessible memory regions, while less frequent programs are stored in other regions. This selective storage strategy ensures that the most critical interruption responses can be executed quickly without requiring the entire buffer to be optimized for maximum speed, thus improving interruption response performance while controlling circuit scale.
Solution Approach 2:
The patent implements partial action by storing only the most frequently occurring interruption programs in the interruption buffer memory, rather than all possible interruption programs. The determination circuit identifies and prioritizes these frequent programs based on occurrence frequency or importance, loading them into the buffer in advance. This partial pre-loading approach provides sufficiently high interruption response performance for common cases while avoiding the need to allocate memory space for every possible interruption scenario, thereby controlling circuit scale.
Data Source
AI summary
An object of the present invention is to provide a semiconductor device and a control method thereof that can suppress a circuit scale from being increased while maintaining a high interruption response performance.According to an embodiment, a semiconductor device includes a flash memory in which N interruption subroutine programs are stored, an interruption control circuit that detects occurrence of an interruption, counters that determine the respective occurrence probabilities of N interruption factors on the basis of the detection result of the interruption control circuit, an interruption buffer memory in which the M (M<N) interruption subroutine programs corresponding to the top M interruption factors determined to be high in the occurrence probability among the N interruption factors are stored, and a CPU that reads, in the case where an interruption of one of the M interruption factors has occurred, the interruption subroutine program corresponding to the interruption from the interruption buffer memory to execute the same.