Semiconductor Device Inversion Control Signal Generation Circuit
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Solution Overview
Problem
Semiconductor devices operating with double data rate (DDR) standards face increased bit error rates as data rate increases, necessitating improved error detection and correction techniques to enhance data transmission reliability.
Innovation Solution
The semiconductor device incorporates an inversion control signal generation circuit, a pattern control signal generation circuit, and a data input/output (I/O) circuit to generate and manage data signals based on address logic levels and test mode signals, allowing for selective inversion and buffering of pre-control signals to optimize data output in various test modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If double data rate (DDR) transfers are used to increase data rate, then data transmission speed is improved, but bit error rate increases
Solution Approach 1:
The patent applies preliminary action by generating test data patterns in advance using the inversion control signal generation circuit and pattern control signal generation circuit. These pre-generated patterns are then used during testing to verify data transmission reliability at high speeds, allowing the system to prepare correction strategies before actual data transmission occurs.
Solution Approach 2:
The patent implements feedback mechanisms through the inversion control signal generation circuit that monitors address logic levels and generates appropriate control signals. This feedback loop ensures that the pattern control signal generation circuit receives accurate information about the current state, allowing it to generate correct test patterns and verify data integrity in real-time during high-speed transmission testing.
2Reliability
If error detection and correction codes are added to improve reliability, then data transmission reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the inversion control signal generation circuit and pattern control signal generation circuit to serve multiple functions. These circuits generate both inversion control signals for error detection and test data patterns for verification, allowing a single circuit structure to perform multiple tasks related to reliability enhancement without proportionally increasing device complexity.
Solution Approach 2:
The patent implements self-service by enabling the inversion control signal generation circuit to automatically generate appropriate control signals based on the logic levels of address signals. The circuit self-regulates the inversion process without external intervention, and the pattern control signal generation circuit automatically generates test patterns based on received control signals, reducing the need for additional complex control mechanisms.
3Productivity
If test data pattern generation time is reduced to improve productivity, then testing efficiency is improved, but measurement precision may be compromised
Solution Approach 1:
The patent applies preliminary action by pre-generating test data patterns using the inversion control signal generation circuit and pattern control signal generation circuit before actual testing. This allows the system to prepare accurate test patterns in advance, then quickly verify them during testing without compromising precision, as the patterns are already computed and ready for immediate use.
Solution Approach 2:
The patent replaces mechanical/time-consuming sequential pattern generation with a more efficient signal processing approach. The inversion control signal generation circuit processes address logic levels and generates inverted control signals through electronic logic operations, which are much faster and more precise than sequential mechanical generation methods, thereby improving both productivity and measurement precision.
Data Source
AI summary
A semiconductor device may include an inversion control signal generation circuit, a pattern control signal generation circuit, and a data input/output (I/O) circuit. The inversion control signal generation circuit may generate an inversion control signal according to a logic level combination of bit patterns included in at least one of a first address and a second address. The pattern control signal generation circuit may generate a pattern control signal from a pre-control signal in response to the inversion control signal. In response to the pattern control signal, the data input/output (I/O) circuit may generate data signals that will be output to an internal I/O line based on data signals loaded on a local I/O line.