Semiconductor I/O Cell Vertical Stacking for EM and ESD Robustness
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Solution Overview
Problem
Semiconductor integrated circuit devices face challenges in reducing the area of I/O cells while maintaining robustness against electro-migration (EM) and electrostatic discharge (ESD), particularly due to the limitations of the PAA technique which reduces the number of metal layers available for peripheral wires, making it difficult to implement staggered arrangements in microcomputer I/O cells with complex functions.
Innovation Solution
The solution involves forming a semiconductor integrated circuit device with a plurality of I/O cells, where power wires are created using multiple interconnect layers over the I/O cells, with bonding pads positioned above these power wires, allowing for high current capacity and robustness against EM and ESD through the use of first and second power wires, each coupled with specific elements and diode elements to manage voltage levels and surge protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the PAA technique is employed to place pads over I/O cells to reduce area, then the area of I/O cells is reduced, but the number of metal layers available for peripheral wires decreases, making it difficult to avoid electromigration and electrostatic discharge
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked configuration by placing bonding pads vertically over I/O cells. This vertical stacking enables area reduction while preserving metal layer resources for peripheral wires, as the pads occupy the vertical dimension rather than consuming additional metal layers for wire routing.
Solution Approach 2:
The patent segments the bonding pad structure into multiple functional layers: the pad electrode layer for electrical connection, the insulating film layer for isolation, and the protective film layer for ESD protection. This segmentation allows each layer to perform its specific function independently, maintaining reliability while achieving area reduction.
2Area of moving object
If the width of I/O cell is reduced to match pad width, then area is reduced, but it becomes difficult to implement staggered arrangement for robustness against electromigration and electrostatic discharge
Solution Approach 1:
The patent resolves the staggered arrangement challenge by moving from horizontal offset positioning to vertical stacking. The bonding pad is positioned directly over the I/O cell in the vertical dimension, eliminating the need for horizontal staggering while maintaining electrical connection and protection functions.
Solution Approach 2:
The patent merges the functions of the bonding pad and I/O cell by positioning them in vertical alignment. The pad electrode, insulating film, and protective film are stacked directly over the I/O cell, combining connection and protection functions in a compact vertical structure that simplifies layout.
3Reliability
If multiple metal layers are used for power wires over I/O cells, then robustness against electromigration and electrostatic discharge is improved, but the number of available metal layers for peripheral wires decreases
Solution Approach 1:
The patent resolves the metal layer conflict by transitioning power wire routing from the horizontal plane to the vertical dimension. Power wires are formed as stacked structures with multiple metal layers vertically aligned over the I/O cell, providing high current capacity and ESD protection without consuming additional horizontal metal layers for peripheral routing.
Solution Approach 2:
The stacked power wire structure serves multiple functions simultaneously: it provides power delivery through multiple parallel metal layers, offers ESD protection through the vertical configuration, and maintains area efficiency by consolidating these functions in the vertical dimension rather than requiring separate horizontal routing resources.
Data Source
AI summary
To provide a semiconductor integrated circuit device advantageous against EM and ESD. A plurality of I/O cells; a power wire formed of a plurality of interconnect layers over the above-described I/O cells; a bonding pad formed in an upper layer of the power wire and in a position corresponding to the I/O cell; and lead-out areas capable of electrically coupling the I/O cell to the bonding pad are provided. The above-described power wire includes a first power wire and a second power wire, and the above-described I/O cell includes first elements coupled to the first power wire and second elements coupled to the second power wire. The first element is placed on the first power wire side, and the second element is placed on the second power wire side. The first power wire and the second power wire can allow for a high current due to the interconnect layers over the I/O cells, thus having robustness against EM and ESD.