Semiconductor Input/Output Circuit Wiring Layout
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing integration density and improving electrical characteristics due to limitations in the arrangement of bumps and input/output areas, which affect the length of wiring patterns and overall device performance.
Innovation Solution
The semiconductor device incorporates a substrate with multiple input/output areas and bumps, where the bumps are connected to input/output pins via upper wiring patterns, allowing for efficient disposition of bumps and reduction in wiring pattern length, thereby enhancing integration density and electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If bumps and input/output areas are disposed in the same area to increase integration density, then the degree of integration is improved, but the wiring pattern length may increase
Solution Approach 1:
The patent utilizes multiple wiring layers (upper wiring patterns and lower wiring patterns) to connect bumps to input/output areas. By distributing wiring connections across different vertical layers, the patent reduces the horizontal wiring length while maintaining integration density, effectively resolving the contradiction between compact arrangement and wiring length.
2Reliability
If the length of wiring patterns connecting bumps and input/output areas is reduced to improve electrical characteristics, then electrical characteristics are improved, but the arrangement flexibility of bumps is limited
Solution Approach 1:
The patent divides the wiring connection into two separate segments: upper wiring patterns for direct bump connections and lower wiring patterns for input/output area connections. This segmentation allows independent optimization of each wiring layer, enabling reduced wiring length for electrical performance while maintaining flexibility in bump arrangement through the multi-layer structure.
3Quantity of substance
If more bumps are disposed in a limited area to increase integration, then the degree of integration is improved, but the wiring complexity increases
Solution Approach 1:
By introducing vertical layering with upper and lower wiring patterns, the patent transforms the two-dimensional wiring layout into a three-dimensional structure. This allows multiple bumps to be connected through different vertical paths, reducing horizontal wiring congestion and complexity while enabling higher bump density in the limited area.
Data Source
AI summary
A semiconductor device includes bumps and a plurality of input/output areas on a substrate. Each of the input/output areas include semiconductor elements on the substrate, lower wiring patterns connected to the semiconductor elements, and input/output pins above and connected to the lower wiring patterns. The semiconductor elements provide a logic circuit and a protection circuit. The bumps are above the lower wiring patterns and connected to the input/output pins by upper wiring patterns. The input/output areas include a first input/output area and a second input/output area. The input/output areas includes a first circuit area including the electrostatic discharge protection circuit and a second circuit area including the logic circuit. In the first input/output area, the input/output pin is in the first circuit area. In the second input/output area, the input/output pin is in the second circuit area.