Semiconductor Ion Implantation for Vertical Horizontal Integration
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Solution Overview
Problem
Existing methods for manufacturing power semiconductor integrated circuits (ICs) with vertically and horizontally integrated elements are inefficient, leading to increased manufacturing time and uneven device characteristics due to multiple high-temperature annealing processes.
Innovation Solution
A method involving multiple ion implantation steps at different acceleration voltages followed by short-period annealing to form ion implantation regions, well regions, and body regions in a semiconductor layer, allowing for the integration of vertical and horizontal power semiconductor elements in a single chip with improved impurity concentration control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple high-temperature annealing processes are conducted to form body region and well region, then impurity ions can be activated, but manufacturing time is significantly increased and impurity concentration becomes uneven
Solution Approach 1:
The patent segments the ion implantation process into multiple steps with different acceleration voltages (e.g., 1.5 MeV for body region, 0.5 MeV for well region) rather than using a single annealing process. This allows selective formation of different regions with controlled impurity concentrations, reducing the need for repeated high-temperature annealing while maintaining uniformity.
Solution Approach 2:
The patent changes the acceleration voltage parameter during ion implantation to control the depth and concentration of impurity ions. By adjusting voltage (e.g., 1.5 MeV vs 0.5 MeV), the same ion implantation process forms different regions (body region vs well region) with different impurity concentrations, eliminating the need for multiple annealing steps.
2Adaptability or versatility
If multiple annealing steps are performed to form different diffusion layers, then various regions can be created, but device characteristics become uneven due to impurity concentration variation
Solution Approach 1:
The patent applies local quality by using different acceleration voltages for different regions: 1.5 MeV for the body region requiring deeper penetration, and 0.5 MeV for the well region requiring shallower implantation. This localized parameter adjustment ensures each region receives the appropriate impurity concentration without affecting other regions, maintaining device characteristic uniformity.
Solution Approach 2:
The patent changes the acceleration voltage parameter to achieve different implantation depths and concentrations in different regions. This parameter variation allows precise control over impurity distribution, creating the necessary region differentiation while avoiding the impurity concentration variation that occurs with multiple annealing steps.
3Ease of manufacture
If conventional ion implantation methods are used, then vertical and horizontal elements can be formed, but integration density remains low and manufacturing efficiency is poor
Solution Approach 1:
The patent merges the formation of body region and well region into a single ion implantation process by using different acceleration voltages in sequence. This combines what would traditionally require separate annealing steps into one integrated process, increasing manufacturing efficiency and enabling higher integration density without sacrificing element formation capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing time, enhances integration density, and improves electrical characteristics by minimizing lateral diffusion and process-derived defects, resulting in a high-density, high-efficiency semiconductor chip.
Implementation Method 1
implanting impurity ions of a second conductivity-type at different implantation positions by multiple implantation in a part of an upper portion of a semiconductor layer
Implementation Method 2
activating the impurity ions in the first ion implantation regions to form a well region of the second conductivity-type, and activating the impurity ions in the second ion implantation regions to form a body region of the second conductivity-type
Data Source
AI summary
A semiconductor integrated circuit includes: implanting impurity ions of a p-type at different implantation positions by multiple implantation in a part of an upper portion of a semiconductor layer of an n−-type to form first ion implantation regions; implanting the impurity ions of the p-type at different implantation positions by multiple implantation in another part of the upper portion of the semiconductor layer to form second ion implantation regions; activating the impurity ions in the first ion implantation regions to form a well region, and activating the impurity ions in the second ion implantation regions to form a body region; forming a control element including first and second terminal regions of the n+-type in an upper portion of the well region; and forming an output-stage element including an output terminal region of the n+-type in an upper portion of the body region to be controlled by the control element.