Semiconductor Ion Implantation Using Silicon Organic Hard Mask
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Solution Overview
Problem
Current semiconductor manufacturing methods for non-volatile memory devices face challenges in precisely defining ion implantation regions and preventing defects in the off-set zero insulation layer during repeated impurity injection processes, especially as transistors become smaller and more integrated.
Innovation Solution
A manufacturing method involving the use of a silicon organic hard mask layer with a good vertical profile for ion implantation, combined with an etch stop layer to protect the off-set zero insulation layer, allowing for precise control of impurity injection and preventing defects during the ion implantation process, enabling the production of transistors with various threshold voltages without process faults.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a photoresistor layer is used as a mask for ion implantation, then the patterning process can be performed, but the vertical profile is poor and manufacturing precision deteriorates
Solution Approach 1:
The patent changes the material parameter of the mask layer from photoresistor to silicon organic material, which inherently provides a superior vertical profile. This material substitution resolves the contradiction by improving the shape parameter (vertical profile) while maintaining or enhancing the manufacturing precision of ion implantation region definition.
Solution Approach 2:
The patent employs a composite mask structure consisting of a silicon organic material layer combined with an etch stop layer. This composite material approach allows the silicon organic layer to provide the vertical profile needed for precise ion implantation, while the etch stop layer protects the underlying OZ insulation layer, thus resolving both the shape and reliability contradictions.
2Adaptability or versatility
If impurity injection is performed repeatedly to create transistors with various threshold voltages, then device functionality is improved, but defects in the off-set zero insulation layer occur
Solution Approach 1:
The patent introduces an etch stop layer as an intermediary protective layer between the mask layer and the OZ insulation layer. This intermediary layer prevents direct contact and damage to the OZ insulation layer during repeated ion implantation processes, allowing the manufacturing of transistors with various threshold voltages while maintaining insulation layer reliability.
Solution Approach 2:
The etch stop layer is formed in advance before the ion implantation process, providing beforehand protection to the OZ insulation layer. This prior cushioning measure ensures that even when impurity injection is performed repeatedly for creating transistors with different threshold voltages, the OZ insulation layer remains intact and free from defects.
3Productivity
If the off-set zero insulation layer is exposed during ion implantation, then ion implantation can be performed, but the insulation layer suffers damage from repeated processes
Solution Approach 1:
The etch stop layer serves as a protective intermediary that allows the ion implantation process to proceed efficiently while preventing damage to the OZ insulation layer. This mediator layer enables repeated ion implantation operations without compromising the reliability of the underlying insulation structure.
Solution Approach 2:
The etch stop layer is formed in advance as a protective barrier before any ion implantation occurs. This preliminary protective action ensures that the OZ insulation layer is shielded from potential damage during the entire ion implantation process, maintaining both productivity and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for precise definition of ion implantation regions and prevents defects in the off-set zero insulation layer, enabling the production of transistors with various threshold voltages on a single substrate, ensuring reliable and fault-free ion implantation processes even when repeated.
Implementation Method 1
injecting first impurities into active fins of the second region; injecting second impurities into the active fins of the first region
Implementation Method 2
preventing defects in the off-set zero insulation layer during repeated impurity injection processes
Implementation Method 3
forming a gate insulation layer between the gate electrodes and the active fins
Data Source
AI summary
Provided is a manufacturing method of a semiconductor device including providing a substrate including a first region and a second region, forming active fins in the first region and the second region, forming gate electrodes which intersect the active fins and have surfaces facing side surfaces of the active fins, forming an off-set zero (OZ) insulation layer covering the active fins, forming a first residual etch stop layer and a first hard mask pattern which cover the first region, injecting first impurities into the active fins of the second region, removing the first hard mask pattern and the first residual etch stop layer, forming second residual etch stop layer and a second hard mask pattern which cover the second region, injecting a second impurities into the active fins of the first region, and removing the second residual etch stop layer and the second hard mask pattern.