Semiconductor IP Test Scheduling for Parallel Diagnosis
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Solution Overview
Problem
As semiconductor chips become highly integrated, testing individual semiconductor IPs with added test logic increases their size and requires significant time and resources, and testing multiple IPs in parallel is desired to reduce total test time, especially when software testing is not allowed.
Innovation Solution
A test device and method that includes a register to store mode and identification data, a fetcher to fetch metadata and instruction data, a driver to communicate with target IPs, and a manager to schedule test operations based on the data, allowing for efficient parallel or sequential testing of multiple semiconductor IPs while reducing resource burden.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If test logic is added to each semiconductor IP, then testing capability is improved, but IP size increases
Solution Approach 1:
The test logic is extracted from individual IPs and consolidated into a centralized test device. Each IP contains only the necessary functionality without embedded test logic, reducing IP size while maintaining testing capability through the external test device that can selectively test any IP.
Solution Approach 2:
The test device is designed as a universal testing platform that can test multiple different semiconductor IPs through a single interface. It uses instruction data stored in memory to control different IP types, making one test device capable of handling various IP configurations without requiring each IP to have dedicated test logic.
2Measurement precision
If individual IP testing is performed, then testing accuracy is improved, but total test time increases
Solution Approach 1:
The test device stores pre-configured instruction data in memory that defines the optimal test sequences for different IP combinations. The manager component uses dependency relationships between IPs to pre-determine the best testing order, allowing the system to automatically execute efficient test sequences without real-time computation delays.
Solution Approach 2:
The test device dynamically adjusts the testing sequence based on dependency relationships between different IPs. The manager component receives dependency information and automatically generates an optimized execution order, allowing the system to adapt to different IP configurations and maximize parallel testing opportunities while maintaining accuracy.
3Productivity
If multiple IPs are tested in parallel, then productivity is improved, but resource requirements increase
Solution Approach 1:
The test device segments the testing process into independent test operations that can be executed in parallel. Each IP can be tested simultaneously using separate test sequences, and the manager component coordinates these parallel operations based on dependency relationships. This segmentation allows multiple IPs to be tested concurrently without requiring additional hardware resources for each parallel test.
Solution Approach 2:
The system changes the temporal parameter of testing by allowing overlapping execution times for different IPs. Through intelligent scheduling based on dependency relationships, the test device optimizes the time distribution of parallel tests, enabling maximum productivity while minimizing resource consumption by reusing test infrastructure across different IP combinations.
Data Source
AI summary
A test device, an electronic device, and an operating method of the test device are provided. The test device schedules an execution order of test operations on target semiconductor intellectual properties (IPs), based on metadata and instruction data, the metadata including a dependency relationship indication between a plurality of semiconductor IPs and a time-out time of the test operation on each of the semiconductor IPs, and the instruction data including an operation and an address of each target semiconductor IP and a test sample, and perform the test operations on the target semiconductor IPs in the scheduled execution order.