Semiconductor Island Pattern Formation Using Spacer Hard Masks
Solution Overview
Problem
The formation of semiconductor device patterns, particularly island and pillar patterns, faces issues with photoresist pattern collapse due to weak adhesion and physical instability, exacerbated by increasing integration density and aspect ratios, leading to reduced yield and reliability.
Innovation Solution
A method involving the formation of a hard mask pattern using a sacrificial layer and spacer formation process, where an amorphous carbon (a-C) layer and SiON layer are used as hard masks, with a polysilicon or TEOS film as a second hard mask material, to etch the underlying layer and create stable island patterns without direct photoresist pattern formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photoresist pattern is used to form island pattern, then pattern formation is achieved, but pattern collapse occurs due to weak adhesion and physical instability
Solution Approach 1:
The patent introduces a sacrificial layer pattern as an intermediary element. This sacrificial layer serves as a temporary structure that enables the formation of the island pattern region without requiring direct photoresist patterning on the final structure. The sacrificial layer is formed through contact hole formation processes and spacer formation, which are more reliable processes. After the hard mask pattern is formed using the sacrificial layer, the sacrificial layer is removed. This intermediary approach transfers the patterning stress to more reliable processes, eliminating the photoresist collapse issue while maintaining manufacturing precision.
2Productivity
If integration density of semiconductor devices is increased, then device functionality is improved, but photoresist pattern collapse becomes more frequent
Solution Approach 1:
The patent segments the pattern formation process into distinct stages: forming the sacrificial layer pattern through contact hole formation, forming spacers, and then forming the hard mask pattern. This segmentation allows each sub-process to be optimized independently. The contact hole formation and spacer formation processes have better process margins and are less susceptible to collapse even at high integration densities. By breaking down the complex photoresist patterning into these simpler, more reliable steps, the patent maintains high integration density while improving pattern formation reliability.
3Manufacturing precision
If aspect ratio of photoresist pattern is increased, then vertical resolution is improved, but pattern collapse increases
Solution Approach 1:
The patent uses a sacrificial layer pattern that is intentionally designed to be temporary and disposable. This sacrificial layer is formed with simple geometry (contact hole pattern) that has excellent structural strength and process margin, regardless of the final island pattern's aspect ratio. The sacrificial layer serves its purpose during hard mask formation and is then completely removed. This approach allows the formation of high aspect ratio island patterns by using a different, more robust temporary structure rather than relying on fragile high aspect ratio photoresist patterns.
Data Source
AI summary
The invention defines a pillar pattern or an island pattern by forming a contact hole and filling the contact hole with a hard mask material by using a spacer formation process, so that the mask pattern formation process margin for island (e.g., pillar) pattern formation is increased. Accordingly, the yield and reliability of the formation process of a semiconductor device are improved.