Semiconductor Apparatus With Island-Shaped Regions
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Solution Overview
Problem
Semiconductor apparatuses face challenges in achieving high switching speed and withstand voltage due to discontinuous depletion layers and curvature-induced electric field concentration, which reduce their performance in applications like power sources and displays.
Innovation Solution
A semiconductor apparatus design featuring a first conductive type semiconductor substrate with a second conductive type region forming a PN junction, aligned islands, and a connecting region, along with an insulating layer and electrodes, reduces curvature and enhances continuous depletion layer integration, improving withstand voltage and switching characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If island-shaped P+-type silicon regions are arranged to form depletion layers, then switching speed is improved, but the depletion layers become discontinuous and withstand voltage reduces
Solution Approach 1:
The P-type silicon region is divided into multiple island-shaped regions arranged in a line, with each island forming a depletion layer. The insulating film is selectively removed at intervals to create contact holes that allow metal electrodes to contact specific islands, enabling the segmented structure to achieve both high switching speed and maintained withstand voltage through proper electrical connection of the segmented regions
Solution Approach 2:
The insulating film is selectively removed only at specific locations to form contact holes, creating local variations in electrical connectivity. This allows certain regions to have direct metal contact (for low resistance) while other regions maintain insulation (for voltage blocking), optimizing both switching speed and withstand voltage in different local areas
2Ease of manufacture
If P+-type silicon regions are formed in island shape, then manufacturing is simplified, but electric field concentrates at curvature portions and withstand voltage reduces
Solution Approach 1:
The invention uses island-shaped regions with curved boundaries, which are easier to manufacture using standard photolithography processes. The curved geometry is optimized to minimize electric field concentration effects while maintaining manufacturing simplicity, achieving a balance between ease of fabrication and electrical performance
3Ease of manufacture
If insulating film is formed on outermost P+-type silicon regions, then electrode contact is controlled, but discontinuous depletion layers reduce withstand voltage
Solution Approach 1:
The insulating film is selectively removed at intervals to create contact holes that expose specific P-type silicon regions. This segmented approach to insulation allows precise control of electrode contact locations while maintaining continuous electrical connection through the metal electrode, thereby maintaining both manufacturing control and high withstand voltage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design reduces electric field concentration, increases withstand voltage, and enhances specific resistance, avalanche, and switching characteristics, bringing the semiconductor apparatus closer to theoretical performance.
Implementation Method 1
depletion layers formed by a PN junction between the N-type silicon region 12 and the island-shaped P+-type silicon regions 15 under a reverse voltage application
Data Source
AI summary
The present invention provides a semiconductor apparatus for improving a switching speed and a withstand voltage, and a manufacturing method of the semiconductor apparatus. The semiconductor apparatus of the invention including a first conductive type semiconductor substrate, a first conductive type first semiconductor region with an impurity concentration lower than that of the semiconductor substrate and formed on a first principal surface of the semiconductor substrate, a second conductive type second semiconductor region formed in a surface region of the first semiconductor region and which forms a PN junction with the first semiconductor region, a contact region including a part of the first semiconductor region and a part of the second semiconductor region, an insulating layer having an opening part through which at least the contact region are exposed, a first electrode formed so as to be in contact with at least the contact region and a second electrode formed on a second principal surface of the semiconductor substrate, wherein the second semiconductor region, viewed from a direction perpendicular to the first principal surface includes a first region in which a plurality of islands of the second semiconductor are aligned with intervals and a second region which connects each end of the islands of the first region each other.