Semiconductor Isolating Feature for GAA Source/Drain Leakage Paths
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Solution Overview
Problem
Integration of gate-all-around (GAA) transistors in semiconductor manufacturing is challenging due to issues with source/drain structures causing off-state leakage current paths when connected directly to the substrate, complicating the manufacturing process.
Innovation Solution
Incorporation of an isolating feature between the source/drain structures and the substrate to prevent direct electrical contact, using methods like epitaxial growth and etching processes to form isolating features made of undoped semiconductor materials or dielectrics, which separate the source/drain structures from the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source/drain structures are directly connected to the substrate, then device fabrication is simpler, but off-state leakage current increases
Solution Approach 1:
An isolating feature is introduced as an intermediary element between the source/drain structures and the substrate. This isolating feature prevents direct electrical contact, thereby blocking off-state leakage current paths while maintaining the overall device structure. The isolating feature acts as a mediator that resolves the contradiction by providing electrical isolation without requiring complete redesign of the fabrication process.
Solution Approach 2:
The device structure is segmented by introducing the isolating feature that divides the direct connection between source/drain structures and substrate into separate regions. This segmentation creates distinct functional zones: one for electrical connection and another for isolation, thereby preventing leakage current while maintaining fabrication feasibility through modular structure design.
2Productivity
If device dimensions are scaled down, then production efficiency improves and costs decrease, but manufacturing process complexity increases
Solution Approach 1:
The isolating feature is formed preliminarily during the fabrication process, specifically within the source/drain recesses before final device assembly. This preliminary action ensures that isolation is built-in from the early stages of manufacturing, preventing leakage current issues that would otherwise require complex post-processing steps or lead to device failure during operation.
3Reliability
If gate-all-around structures are implemented, then gate control is improved, but integration fabrication becomes challenging
Solution Approach 1:
The isolating feature is specifically positioned at the source/drain-substrate interface, providing localized electrical isolation precisely where leakage current paths occur. This local quality approach addresses the fabrication challenge by applying isolation only in critical regions rather than throughout the entire device structure, thereby maintaining gate-all-around control while simplifying integration fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces off-state leakage current, enhancing the performance and reliability of GAA transistors by minimizing current leakage and maintaining device integrity during scaling.
Implementation Method 1
Incorporation of an isolating feature between the source/drain structures and the substrate to prevent direct electrical contact
Data Source
AI summary
Semiconductor structures and methods for manufacturing the same are provided. The method includes forming a fin structure with first semiconductor material layers and second semiconductor material layers alternately stacked over a substrate and forming fin spacers on sidewalls of the fin structure. The method further includes etching the fin structure to form a source/drain recess exposing inner sidewalls of the fin spacers and forming an isolating feature covering lower portions of the inner sidewalls of the fin spacers. The method further includes forming a source/drain structure covering upper portions of the inner sidewalls of the fin spacers and removing the first semiconductor material layers. The method further includes forming a gate structure wrapping around the second semiconductor material layers.