Semiconductor Isolation Etching for Low-Stress CPODE Integration
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, challenges arise in maintaining isolation between adjacent devices and reducing epitaxial layer stress during fabrication, particularly in the CPODE process, which affects integration density and device performance.
Innovation Solution
The implementation of a Continuous Poly On Diffusion Edge (CPODE) process, where a plasma etching process is used to form a cut region between adjacent active edges and fill it with dielectric material like silicon nitride, providing isolation and self-aligning structures, while being performed after metal gate formation to reduce stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional etching processes are used to form isolation regions, then isolation between devices is achieved, but epitaxial layer stress increases and overlay precision deteriorates
Solution Approach 1:
The patent performs etching to form isolation regions before forming the epitaxial layer, rather than after. This preliminary action prevents the etching process from inducing stress in the already-formed epitaxial layer, thereby maintaining device reliability while avoiding stress-related performance degradation.
Solution Approach 2:
The patent segments the fabrication process into distinct stages: first forming isolation regions through etching, then forming the epitaxial layer separately. This segmentation allows each process to be optimized independently, ensuring that the etching process provides effective isolation without adversely affecting the stress state of the subsequent epitaxial layer.
2Productivity
If feature size is reduced to increase integration density, then more components fit in given area, but maintaining isolation between adjacent devices becomes more difficult
Solution Approach 1:
The patent forms isolation regions before forming the epitaxial layer and performing subsequent processing steps. This preliminary establishment of isolation structures ensures that even as feature sizes are reduced, the isolation regions are already in place to prevent electrical interference between adjacent devices, maintaining reliability despite higher integration density.
3Reliability
If CPODE process is performed before metal gate formation, then isolation is provided, but overlay tolerance decreases and stress increases
Solution Approach 1:
The patent inverts the conventional sequence by forming isolation regions before metal gate formation rather than after. This reversal of the process sequence allows the metal gate to be self-aligned to the isolation regions, improving overlay tolerance while maintaining effective isolation between devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances overlay tolerance, reduces epitaxial layer stress, and improves isolation between devices, leading to increased integration density and improved device performance by maintaining effective insulation and reducing current leakage.
Implementation Method 1
performing a plasma etching process to etch the fins and the isolation regions
Implementation Method 2
wherein the plasma etching process chemically etches the fins
Implementation Method 3
wherein the plasma etching process physically etches the isolation regions
Data Source
AI summary
Semiconductor devices and methods of fabrication are provided. A method includes providing a semiconductor structure with a first sidewall distanced from a second sidewall, fins located between the first sidewall and the second sidewall, and isolation regions located between the first sidewall and the second sidewall, wherein adjacent fins are separated by a respective isolation region. The method further includes performing a plasma etching process to etch the fins and the isolation regions, wherein the plasma etching process chemically etches the fins, wherein the plasma etching process physically etches the isolation regions to recesses defining a crown-shaped depth profile.