Semiconductor Isolation Structure With Crack-Resistant Dielectric Layers
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Solution Overview
Problem
Semiconductor structures face defects due to cracking of isolation structures and dielectric liners during fabrication, leading to short circuits in conductive structures.
Innovation Solution
A method involving the formation of a dielectric liner and cap layer on isolation structures to prevent cracking, using materials like silicon oxide and silicon nitride, and employing processes such as chemical vapor deposition and thermal annealing to harden these layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If isolation structures and dielectric liners are formed during semiconductor fabrication, then the semiconductor structure can be constructed, but thermal stress causes cracking and defects
Solution Approach 1:
The patent divides the isolation structure into multiple segments by forming alternating regions of first dielectric material and second dielectric material with different stress characteristics. This segmentation allows the structure to accommodate thermal stress differentials, preventing cracking while maintaining the isolation function.
Solution Approach 2:
The patent employs composite dielectric structures combining different dielectric materials with contrasting thermal stress properties. The first dielectric material has higher thermal stress and the second has lower thermal stress, creating a composite system that balances overall stress and prevents cracking during fabrication and operation.
2Device complexity
If conventional isolation structures are formed without stress-balancing layers, then the fabrication process is simpler, but cracking occurs leading to short circuits
Solution Approach 1:
The patent applies beforehand cushioning by incorporating stress-balancing dielectric layers during the formation of isolation structures, anticipating and preventing thermal stress cracking before it occurs. This proactive approach cushions the structure against future thermal stress, eliminating the need for complex repair processes.
3Strength
If dielectric liners are coated on isolation structures, then the structure integrity is improved, but thermal stress from subsequent processes causes cracking
Solution Approach 1:
The patent changes the stress parameters of the dielectric structure by incorporating materials with different thermal stress characteristics in alternating layers. This parameter variation allows the structure to accommodate thermal expansion and contraction differently across layers, preventing crack propagation while maintaining overall integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents cracking of isolation structures, improving the yield and uniformity of semiconductor structures by maintaining the integrity of the semiconductor layer and reducing defects.
Implementation Method 1
employing processes such as chemical vapor deposition
Implementation Method 2
employing processes such as chemical vapor deposition and thermal annealing to harden these layers
Data Source
AI summary
The method of forming the semiconductor structure includes the following steps. First trenches and second trenches are respectively formed in a substrate of the logic region and the substrate of the array region. A dielectric liner is formed in the first trenches and second trenches. First coating blocks and second coating blocks are respectively formed in the first trenches and second trenches. A cap layer is formed on the first coating blocks and the second coating blocks. Oxide structures are formed on the cap layer. Part of the oxide structures and part of the cap layer is removed. A semiconductor layer is formed in the array region and disposed on the substrate and between the oxide structures.