Semiconductor Isolation Structure Curvature Control

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Solution Overview

Problem

Current high-voltage semiconductor devices face limitations in isolation structure formation, leading to unsatisfactory performance in certain applications, particularly in high-voltage and high-power integrated circuits, where curvature profiles impact gate oxide integrity and electronic quality.

Innovation Solution

A method is developed to form isolation structures with specific curvature profiles by patterning dielectric layers, depositing cap layers, and performing oxidation processes to create oxide regions with distinct curvatures, thereby improving gate oxide integrity and electronic quality without affecting low-voltage area performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional isolation structures are used in high-voltage semiconductor devices, then manufacturing simplicity is maintained, but gate oxide integrity and electronic quality deteriorate due to unfavorable curvature profiles

Engineering Contradiction:
Improvegate oxide integrityVSAvoidisolation structure formation process
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The isolation structure formation process is segmented into distinct regions: a first area with a first curvature profile and a second area with a second curvature profile. This segmentation allows each region to be optimized independently for its specific functional requirements, resolving the contradiction between reliability and process complexity by creating region-specific curvature profiles that improve gate oxide integrity without requiring complete redesign of the entire isolation structure

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different curvature profiles are applied to different areas of the isolation structure based on local requirements. The first area has a first curvature optimized for its specific needs, while the second area has a second curvature optimized for its requirements. This local quality approach improves gate oxide integrity in each region without compromising the overall device performance, effectively resolving the contradiction between reliability improvement and process complexity

Inventive Principle:
Principle #3Local quality

2Reliability

If curvature profiles are optimized for high-voltage areas, then gate oxide integrity improves, but low-voltage area performance may be affected

Engineering Contradiction:
Improveelectronic quality in high-voltage areasVSAvoidperformance across different voltage areas
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent applies different curvature profiles to different voltage areas: the first area has a first curvature profile optimized for high-voltage performance, while the second area has a second curvature profile optimized for low-voltage performance. This local optimization ensures that each area achieves its best possible electronic quality without compromising the other, effectively resolving the contradiction between specialized optimization and overall adaptability

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The isolation structure is divided into segmented regions with distinct curvature profiles tailored to specific voltage requirements. This segmentation allows the high-voltage area to benefit from curvature optimization for gate oxide integrity while the low-voltage area maintains its performance characteristics, thus resolving the contradiction between specialized optimization and versatility

Inventive Principle:
Principle #1Segmentation

3Productivity

If uniform isolation structures are formed across all areas, then manufacturing simplicity is maintained, but performance in specific high-voltage applications deteriorates

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidperformance in high-voltage applications
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements local quality by forming isolation structures with different curvature profiles in different areas. The first area has a first curvature profile optimized for high-voltage performance, while the second area has a second curvature profile for its specific requirements. This localized optimization improves high-voltage performance without requiring complete redesign of the manufacturing process, thus resolving the contradiction between manufacturing efficiency and specialized performance

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent employs preliminary action by forming cap layers with different thicknesses in different areas before the oxidation process. The thicker cap layer in the first area and thinner cap layer in the second area are prepared in advance to achieve the desired curvature profiles after oxidation. This preliminary preparation enables differentiated curvature formation without significantly complicating the manufacturing process, resolving the contradiction between productivity and reliability

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method enhances gate oxide integrity and electronic quality in high-voltage areas while maintaining performance in low-voltage areas by controlling curvature profiles, resulting in improved semiconductor device performance.

Implementation Method 1

performing an oxidation process on the second area to form a first oxide region over the sidewall of the second isolation structure and under the bottom surface of the patterned dielectric structure of the second area

Methodology Applied
Scientific EffectOxidation: Oxidation

Data Source

PatentUS10418282B2Methods for forming the isolation structure of the semiconductor device and semiconductor devices
Publication Date: 2019.09.17 VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
  • US10418282B2 patent drawing
  • US10418282B2 patent drawing
  • US10418282B2 patent drawing

AI summary

A method for forming an isolation structure of a semiconductor device is provided. The method includes forming a patterned dielectric structure in a first area and a second area of a substrate; forming a first isolation structure in the first area and forming a second isolation structure in the second area of the substrate; forming a cap layer over the first area and the second area of the substrate and performing an etching process to etch the cap layer of the second area completely; and performing an oxidation process on the second area to form a first oxide region over the second isolation structure and under the bottom surface of the patterned dielectric structure of the second area.