Semiconductor Isolation Structure for Cut Metal Gate Separation
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Solution Overview
Problem
As semiconductor devices shrink in size, the lithography process in the cut poly gate scheme often fails to completely expose the selected poly gate structure, leading to reduced yield and IC failures due to incomplete separation of metal gate lines between transistors.
Innovation Solution
A cut metal gate (CMG) scheme is introduced, where an isolation structure with footing structures is formed between adjacent fin structures on a substrate, utilizing insulating materials with high etching selectivity to effectively separate gate metal lines, preventing transistor failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If transistor sizes are scaled down to increase storage capacity and processing speed, then device performance is improved, but manufacturing complexity increases and isolation between gate metal lines becomes difficult to achieve
Solution Approach 1:
The isolation structure is divided into multiple functional regions: a first insulating material region filling space between fin structures, and a second insulating material region filling space above the first region. This segmentation allows different etching rates to be utilized in different zones, enabling effective isolation of gate metal lines while managing manufacturing complexity through systematic process division.
Solution Approach 2:
Different regions of the isolation structure use insulating materials with different etching rates. The first insulating material has a first etching rate while the second insulating material has a second etching rate, creating local quality variations that enable selective isolation. This allows the gate metal lines to be effectively separated in critical areas while maintaining structural integrity elsewhere.
2Area of moving object
If transistor sizes are scaled down, then device density increases, but electrical isolation between adjacent transistors becomes insufficient leading to transistor failures
Solution Approach 1:
The isolation structure extends into the vertical dimension with the second insulating material region positioned above the first insulating material region. This three-dimensional configuration provides enhanced electrical isolation between adjacent transistors beyond what planar isolation could achieve, thereby improving reliability while supporting high device density through vertical space utilization.
Solution Approach 2:
The isolation structure employs a composite configuration of two different insulating materials with different etching rates. This composite approach enables the first insulating material to provide base isolation while the second insulating material provides enhanced isolation in critical areas, achieving reliable electrical separation between densely packed transistors.
3Ease of manufacture
If conventional isolation structures are used without footing regions, then manufacturing is simpler, but gate metal lines cannot be effectively isolated leading to IC failures
Solution Approach 1:
The first insulating material is deposited and planarized before the second insulating material is deposited. This preliminary action creates a stable base layer that facilitates the subsequent deposition and etching processes, enabling effective gate metal line isolation while maintaining manufacturing feasibility through systematic process sequencing.
Solution Approach 2:
The first insulating material acts as an intermediary layer between the fin structures and the second insulating material. This intermediate layer provides a platform for the second insulating material and enables selective etching to isolate gate metal lines, serving as a mediator that makes the overall isolation process manufacturable and reliable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The CMG scheme enhances the separation of gate metal lines, improving the reliability and yield of semiconductor devices by ensuring complete isolation, thus addressing the limitations of the cut poly gate scheme.
Implementation Method 1
employing insulating materials with selective etching rates to separate gate metal lines between fin structures
Data Source
AI summary
The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and an isolation structure between the first and second vertical structures. The isolation structure can include a center region and footing regions formed on opposite sides of the center region. Each of the footing regions can be tapered towards the center region from a first end of the each footing region to a second end of the each footing region.