Semiconductor Isolation Region Lateral Diffusion Control
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Solution Overview
Problem
Conventional methods for forming isolation regions in semiconductor integrated circuits using thermal diffusion of impurities result in large horizontal pattern areas, hindering the miniaturization of semiconductor devices due to lateral diffusion.
Innovation Solution
A method involving the formation of recesses in semiconductor substrates and insulation films, followed by selective impurity implantation and thermal diffusion, where phosphorus compensates boron impurities to suppress lateral extension, resulting in impurity profiles with narrower upper ends and wider lower ends, reducing horizontal pattern areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If impurities are introduced into the semiconductor substrate and thermally diffused to form an isolation region, then the isolation region can electrically isolate the well region and semiconductor elements, but the lateral diffusion causes a large horizontal pattern area that makes reducing the size of the semiconductor integrated circuit difficult
Solution Approach 1:
The isolation region formation process is segmented into multiple steps: first forming a first impurity region with one type of impurity, then forming a second impurity region with opposite polarity impurity adjacent to it. This segmentation allows control over the diffusion profile to reduce lateral extension while maintaining electrical isolation functionality.
Solution Approach 2:
The patent applies different impurity types and concentrations at different locations within the isolation region. The first impurity region and second impurity region have opposite polarities and are distributed differently, creating local quality variations that suppress lateral diffusion while ensuring effective electrical isolation at the boundaries.
2Quantity of substance
If thermal diffusion is used to form the isolation region, then impurities can be effectively introduced and distributed, but the lateral diffusion along with vertical diffusion increases the horizontal pattern area
Solution Approach 1:
The patent changes the parameters of impurity introduction by using sequential ion implantation with different impurity types, doses, and energies. By controlling the implantation conditions and thermal diffusion parameters, the vertical diffusion is enhanced while lateral diffusion is suppressed, reducing the horizontal pattern area.
Solution Approach 2:
The isolation region is formed as a composite structure with two different impurity regions having opposite polarities. This composite impurity distribution creates internal electric fields that suppress lateral diffusion, allowing effective impurity distribution vertically while minimizing horizontal extension.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the size of semiconductor integrated circuits by minimizing the lateral extension of impurity diffusion regions, allowing for smaller pattern areas and more compact device designs while maintaining secure isolation.
Implementation Method 1
forming a first impurity region of a second general conductivity type in the surface portion of the semiconductor substrate by introducing impurities into part of the surface portion
Implementation Method 2
thermally diffusing the impurities in the first impurity region and the impurities in the second impurity region so as to form an impurity diffusion region
Data Source
AI summary
A semiconductor integrated circuit is reduced in size by suppressing lateral extension of an impurity region when impurities in the impurity region are thermally diffused in a semiconductor substrate. A second photoresist is formed on an insulation film. The second photoresist is formed to have second openings K2 on both sides of a P-type impurity region so that the second openings K2 partially overlap the P-type impurity region. The insulation film is etched off together with an underlying surface of the semiconductor substrate using the second photoresist as a mask so as to remove the P-type impurity region partially. Then, phosphorus ions (P+) are implanted into the surface of the semiconductor substrate in the etched-off regions using the second photoresist as a mask to form N-type impurity regions that are adjacent the P-type impurity region. After removing the second photoresist, the impurities in the P-type impurity region and the impurities in the N-type impurity region are thermally diffused.