Semiconductor Isolation Layout for ESD Noise Tolerance
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Solution Overview
Problem
Conventional semiconductor devices face a reduction in noise tolerance due to the fluctuation of substrate potential caused by electrostatic discharge (ESD) and displacement current, which leads to parasitic operations, especially when the low-side circuit is close to the n-type well region.
Innovation Solution
A semiconductor device configuration is introduced, featuring a substrate body with a first conductivity-type well region, a voltage blocking region of a second conductivity-type with lower impurity concentration, a contact region with higher impurity concentration, and an isolation region to electrically isolate the voltage blocking region from the low-side circuit, along with level shifters for signal transmission between high-side and low-side circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the low-side circuit is located close to the n-type well region, then chip area is reduced, but substrate potential fluctuation transmits to induce parasitic operation and reduce noise tolerance
Solution Approach 1:
The voltage blocking region is divided into a first voltage blocking region (n-type) and a second voltage blocking region (p-type) arranged in sequence from the n-type well region toward the low-side circuit. This segmentation creates multiple isolation barriers that prevent substrate potential fluctuation from transmitting to the low-side circuit, thereby maintaining noise tolerance while allowing compact layout.
Solution Approach 2:
The first and second voltage blocking regions act as intermediary structures between the n-type well region and the low-side circuit. These regions with different conductivity types create potential barriers that block the transmission of parasitic signals and substrate potential fluctuations, protecting the low-side circuit while maintaining close proximity for area efficiency.
2Strength
If the first voltage blocking region has lower impurity concentration, then voltage blocking capability is improved, but the region becomes more susceptible to potential rise from displacement current
Solution Approach 1:
The voltage blocking function is segmented between two regions with different impurity concentrations and conductivity types. The first voltage blocking region (n-type, lower impurity concentration) provides high voltage blocking capability, while the second voltage blocking region (p-type, higher impurity concentration) provides resistance to potential rise from displacement current, creating a complementary isolation system.
Solution Approach 2:
The isolation structure uses a composite configuration of n-type and p-type semiconductor regions with different impurity concentrations. This composite structure combines the advantages of each region type: the n-type region provides excellent voltage blocking, while the p-type region provides stability against displacement current effects, achieving both goals simultaneously.
3Reliability
If the contact region has higher impurity concentration, then electrical contact is improved, but the region generates more displacement current during potential transitions
Solution Approach 1:
The contact region is designed with locally high impurity concentration specifically at the interface with the voltage blocking region to ensure excellent electrical contact and low contact resistance. The higher impurity concentration is confined to this specific location rather than throughout the entire contact structure, minimizing displacement current generation while maintaining contact quality.
Data Source
AI summary
A semiconductor device includes: a substrate body of a first conductivity-type; a first well region of a second conductivity-type provided in the substrate body and provided with a high-side circuit; a first voltage blocking region of the second conductivity-type provided around the first well region; a contact region of the second conductivity-type provided at an upper part of the first well region or the first voltage blocking region; a second voltage blocking region of the first conductivity-type provided on an outer circumferential side of the first voltage blocking region so as to be in contact with the first voltage blocking region; a first isolation region of the first conductivity-type provided to electrically isolate, from the first well region, an opposed part of the first voltage blocking region opposed to a low-side circuit provided on an outer circumferential side of the second voltage blocking region; and a level shifter.