Semiconductor Isolation Structure for Low-Aspect-Ratio Gate Cutting
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Solution Overview
Problem
The scaling down of semiconductor devices increases complexity in the CMG process due to high aspect ratios of gate structures, making it challenging to remove redundant gate portions and form effective isolation structures, which can lead to performance variability and increased manufacturing costs.
Innovation Solution
The formation of isolation structures with smaller aspect ratios than gate structures, allowing for the simultaneous cutting of multiple long gate structures, and using these structures as etch stop layers to control S/D contact height, thereby improving fabrication process control and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate structures are scaled down to increase storage capacity and processing speed, then device performance is improved, but the aspect ratio of gate structures increases making the CMG process more complex
Solution Approach 1:
The patent segments the gate structure into multiple sections by introducing isolation structures between adjacent gate portions. This segmentation allows each gate section to be independently processed with lower aspect ratios, reducing the complexity of the CMG process while maintaining the scaled-down dimensions for improved device performance
Solution Approach 2:
The patent introduces isolation structures as intermediary elements between adjacent gate structures. These isolation structures serve as mediators that enable the cutting and separation of gate portions while managing the aspect ratio challenge, thus reducing CMG process complexity without compromising device performance
2Length of moving object
If the aspect ratio of gate structures is high, then device scaling is achieved, but it becomes difficult to remove redundant gate portions and form effective isolation structures
Solution Approach 1:
The patent divides the continuous gate structure into segmented portions using isolation structures. This segmentation reduces the effective aspect ratio of each gate section, making it easier to remove redundant gate portions and form effective isolation structures compared to attempting to process a single high aspect ratio gate structure
Solution Approach 2:
The patent introduces an additional dimensional consideration by forming isolation structures that extend in a direction perpendicular to the gate length. This dimensional approach allows the creation of isolation regions that effectively separate gate portions without requiring extreme aspect ratio reduction in the primary gate direction
3Manufacturing precision
If isolation structures are formed with smaller aspect ratios, then CMG process control is improved, but additional process steps are required to simultaneously cut multiple gate structures
Solution Approach 1:
The patent merges the isolation structure formation with the gate cutting process by using the same etch process to simultaneously create both the isolation structures and separate the gate portions. This merging of operations improves CMG process control through smaller aspect ratios while consolidating process steps to offset the increased complexity
Data Source
AI summary
A semiconductor device with an isolation structure and a method of fabricating the same are disclosed. The semiconductor device includes first and second fin structures disposed on a substrate and first and second pairs of gate structures disposed on the first and second fin structures. The first end surfaces of the first pair of gate structures face second end surfaces of the second pair of gate structure. The first and second end surfaces of the first and second pair of gate structures are in physical contact with first and second sidewalls of the isolation structure, respectively. The semiconductor device further includes an isolation structure interposed between the first and second pairs of gate structures. An aspect ratio of the isolation structure is smaller than a combined aspect ratio of the first pair of gate structures.