Semiconductor Isolation Structure With Low-Aspect-Ratio Gate Separation
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Solution Overview
Problem
The scaling down of semiconductor devices increases complexity in the CMG process due to high aspect ratios of gate structures, making it challenging to remove redundant gate portions and form effective isolation structures, which affects device performance and manufacturing costs.
Innovation Solution
The formation of isolation structures with smaller aspect ratios than gate structures, allowing for simplified etching and faster deposition, and extending into the substrate to provide electrical isolation between p- and n-well regions, used as an etch stop layer to control S/D contact structure height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate structures are scaled down to increase storage capacity and processing speed, then device performance is improved, but the aspect ratio of gate structures increases making the CMG process more complex
Solution Approach 1:
The patent divides the gate structure into multiple segments by introducing mandrel structures between adjacent gates. This segmentation allows the CMG process to be broken down into manageable steps: forming mandrels, depositing first spacers, removing mandrels, depositing second spacers, and selectively etching. The segmentation principle transforms the complex high-aspect-ratio gate structure into a multi-stage fabrication process with lower individual step complexities.
Solution Approach 2:
The patent applies preliminary action by pre-forming mandrel structures and first spacer layers before finalizing the gate structure. These preliminary elements serve as templates and guides for subsequent processing steps, enabling precise control over gate dimensions and spacing while reducing the complexity of the overall CMG process.
2Volume of moving object
If the aspect ratio of gate structures is increased due to scaling, then device density is improved, but the ability to remove redundant gate portions deteriorates
Solution Approach 1:
The patent introduces mandrel structures as intermediary elements that facilitate the removal of redundant gate portions. The mandrels act as sacrificial placeholders that define the final gate positions, allowing redundant gate material to be systematically removed through selective etching processes. The first and second spacers serve as additional intermediaries that transfer the pattern from mandrels to final gate structures.
Solution Approach 2:
The preliminary formation of mandrels and spacer structures creates a controlled framework that guides the removal process. By establishing these preliminary structures, the patent enables systematic removal of redundant gate portions through selective etching, transforming a difficult high-aspect-ratio removal task into a series of controlled, lower-aspect-ratio etching steps.
3Reliability
If isolation structures are formed with high aspect ratios to match gate structures, then electrical isolation is achieved, but deposition time and manufacturing cost increase
Solution Approach 1:
The patent changes the aspect ratio parameter of isolation structures by forming them at a lower aspect ratio than the gate structures. This is achieved through the multi-stage spacer formation process, where the isolation structures are defined by the interaction of mandrels and spacers rather than directly by high-aspect-ratio etching. The parameter change from high to lower aspect ratio reduces deposition time and manufacturing cost while maintaining effective electrical isolation through the dielectric material properties.
Data Source
AI summary
A semiconductor device with an isolation structure and a method of fabricating the same are disclosed. The semiconductor device includes first and second fin structures disposed on a substrate and first and second pairs of gate structures disposed on the first and second fin structures. The first end surfaces of the first pair of gate structures face second end surfaces of the second pair of gate structure. The first and second end surfaces of the first and second pair of gate structures are in physical contact with first and second sidewalls of the isolation structure, respectively. The semiconductor device further includes an isolation structure interposed between the first and second pairs of gate structures. An aspect ratio of the isolation structure is smaller than a combined aspect ratio of the first pair of gate structures.