Semiconductor Isolation Structure With Graded Diffusion Layers
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Solution Overview
Problem
Conventional semiconductor devices face challenges in reducing device size due to the wide diffusion of P-type diffusion layers, which are not effectively suppressed, especially when in contact with low-concentration N-type regions, and require lengthy heat treatment, making it difficult to achieve smaller dimensions.
Innovation Solution
The semiconductor device employs a structure where first conduction type diffusion layers, formed from the surface of the semiconductor layer with varying impurity concentrations, are coupled with second conduction type diffusion layers to form isolation regions, thereby suppressing the widthwise diffusion of the first conduction type diffusion layers and improving withstand voltage characteristics by placing the lowest impurity concentration diffusion layer at the periphery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a P type diffusion layer is used to form the isolation region in contact with the lowest-concentration N type region, then the isolation region can be formed, but the diffusion layer diffuses widely in the width direction and cannot suppress extension of diffusion
Solution Approach 1:
The patent applies local quality by creating a concentration gradient within the diffusion layer, where the impurity concentration varies from the surface toward the deeper region. Specifically, the diffusion layer has lower impurity concentration near the surface and higher concentration in the deeper region, allowing different zones to serve different functions: the low-concentration zone suppresses lateral diffusion at the interface, while the high-concentration zone provides adequate isolation and reduces resistance in the bulk region.
2Reliability
If a P type buried diffusion layer with high impurity concentration is used, then the isolation region can be formed, but it requires long heat treatment time which increases device size
Solution Approach 1:
The patent segments the diffusion layer into multiple regions with different impurity concentrations along the depth direction. Instead of using a single uniform high-concentration layer that requires prolonged heat treatment, the structure divides the diffusion region into a surface proximity zone with lower concentration and a deeper zone with higher concentration, enabling faster processing while maintaining isolation effectiveness.
3Reliability
If the impurity concentration in the first conduction type diffusion layer is increased to reduce resistance, then the withstand voltage characteristics deteriorate
Solution Approach 1:
The patent applies local quality by spatially varying the impurity concentration within the diffusion layer. The region near the PN junction interface maintains lower impurity concentration to ensure adequate breakdown voltage and prevent premature avalanche breakdown, while the deeper regions and central areas have higher impurity concentration to provide low-resistance current paths and reduce overall isolation region resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for reduced device size by controlling the diffusion of isolation regions, enhanced withstand voltage characteristics, and lower resistance, while preventing surface inversion due to metal wiring.
Implementation Method 1
a P type diffusion layer is diffused by a thermal diffusion method in a direction of the depth and in a direction of the width of the substrate and the epitaxial layer
Implementation Method 2
The P type diffusion layer is diffused by a thermal diffusion method
Data Source
AI summary
In a semiconductor device of the present invention, an N type epitaxial layer is formed on a P type single crystal silicon substrate. The substrate and the epitaxial layer are partitioned into a plurality of element formation regions by isolation regions. Each of the isolation regions is formed of a P type buried diffusion layer and a P type diffusion layer coupled thereto. The P type buried diffusion layer is joined to N type buried diffusion layers on both sides thereof to form PN junction regions. On the other hand, the P type diffusion layer is joined to N type diffusion layers on both sides thereof to form PN junction regions. This structure suppresses extension of widthwise diffusion of the P type buried diffusion layer and the P type diffusion layer, thus making it possible to reduce the device size.