Semiconductor Device Isolation Height for Leakage Prevention
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Solution Overview
Problem
In semiconductor devices with small channel widths, the margin for misalignment of contact holes over active regions is reduced, leading to a risk of electrical short-circuiting and leakage current due to the proximity of contact plugs to well regions, especially when the element isolation insulating film height is low.
Innovation Solution
The semiconductor device incorporates a structure with distinct active regions defined by different element isolation insulating films, where the etching stopper films and interlayer insulating films are used to form plugs that reach these regions, ensuring the contact holes are properly aligned and preventing leakage current by maintaining a secure distance from the well regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the element isolation insulating film height is lowered to secure channel width in small-scale MIS transistors, then the channel width is improved, but the margin for contact hole misalignment is reduced and leakage current increases
Solution Approach 1:
The patent introduces a height dimension differentiation by forming the first element isolation insulating film higher than the second element isolation insulating film. This vertical dimensional change creates additional isolation space in the height direction, compensating for the reduced horizontal margin caused by small channel widths, and prevents contact hole misalignment from causing leakage current.
Solution Approach 2:
The patent applies different heights to element isolation insulating films in different regions: the first element isolation insulating film in the memory cell region is formed higher than the second element isolation insulating film in the peripheral circuit region. This local quality differentiation provides enhanced isolation where needed (memory cell region with smaller channel width) while maintaining standard isolation in other regions.
2Productivity
If the channel width is reduced for device scaling, then the device density is improved, but the margin for contact hole misalignment becomes small leading to potential short-circuiting
Solution Approach 1:
By increasing the height of the first element isolation insulating film relative to the second element isolation insulating film, the patent creates additional vertical isolation space. This dimensional change provides a larger safety margin for contact hole alignment in the vertical direction, compensating for the reduced horizontal alignment margin caused by smaller channel widths in high-density devices.
Solution Approach 2:
The patent implements region-specific isolation heights where the memory cell region (requiring higher device density) has a higher first element isolation insulating film, while the peripheral circuit region maintains a standard second element isolation insulating film height. This local quality approach enables high-density packaging while maintaining adequate manufacturing precision margins where needed.
Data Source
AI summary
In a memory cell region of a semiconductor device, a memory active region is defined by an element isolation insulating film. In the memory cell region, the position of the upper surface of the element isolation insulating film is set to be lower than the position of the main surface of a semiconductor substrate. A buried silicon nitride film and an etching stopper film are formed over the element isolation insulating film. The position of the upper surface of the etching stopper film is higher than that of the upper surface of the element isolation insulating film defining a peripheral active region.