Semiconductor Device Void Prevention via Isolation Height Offset
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor devices, the advancement of microfabrication leads to short circuits between contact plugs due to voids formed in the interlayer insulating film, causing metal films to be buried in these voids and resulting in electrical shorts, especially when the distance between patterns on the substrate is reduced.
Innovation Solution
A semiconductor device design where the upper surface of the element isolation region is positioned lower than the main surface of the semiconductor substrate, preventing voids from connecting contact plugs by forming the voids at a position lower than the conductive films, thus preventing metal films from being buried in these voids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the distance between patterns on the substrate is reduced to advance microfabrication, then the integration density is improved, but voids are formed in the interlayer insulating film causing short circuits between contact plugs
Solution Approach 1:
The invention introduces a height dimension difference between the element isolation region upper surface and the semiconductor substrate main surface. By positioning the element isolation region upper surface lower than the main surface, it creates a vertical offset that prevents void formation in the interlayer insulating film, thus solving the short circuit problem while maintaining reduced pattern distances.
Solution Approach 2:
The element isolation region is formed with its upper surface positioned lower than the main surface before forming the interlayer insulating film. This preliminary height difference prevents voids from forming between adjacent patterns when the insulating film is deposited, thereby preventing future short circuits between contact plugs.
2Stability of the object's composition
If the interlayer insulating film is formed to cover closely spaced patterns, then the film coverage is improved, but voids are formed between adjacent patterns leading to metal film burial and short circuits
Solution Approach 1:
By creating a height difference in the vertical dimension between the element isolation region and the substrate surface, the invention enables complete film coverage without void formation. The lower element isolation region upper surface ensures that the interlayer insulating film can be continuously deposited without creating air gaps or voids between adjacent patterns.
3Reliability
If contact holes are formed to penetrate through the interlayer insulating film, then the electrical connection is enabled, but metal films are buried in voids causing short circuits between contact plugs
Solution Approach 1:
The invention extracts or removes the harmful voids from the interlayer insulating film by creating a height difference with the element isolation region. By positioning the element isolation region upper surface lower than the main surface, voids are prevented from forming at the level where contact holes are formed, thus eliminating the source of short circuits while maintaining electrical connectivity.
Data Source
AI summary
When a void is caused in an interlayer insulating film on a semiconductor substrate, the invention prevents short circuit between two or more contact plugs that sandwich the void therebetween via a conductive film buried in the void at the time of formation of the contact plugs. An element isolation region having an upper surface lower than a main surface of the semiconductor substrate is formed inside a trench in the main surface of the semiconductor substrate, so that a void formed immediately above the semiconductor substrate in an active region and a void formed immediately above the element isolation region are divided from each other. In this manner, a conductive film is prevented from being buried in the second void.