Semiconductor Isolation Support Structure to Prevent ILD Dishing
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Solution Overview
Problem
Current semiconductor structures face performance inadequacies due to top surface dishing and reduced thickness of the interlayer dielectric layer above isolation structures, leading to potential contact with source/drain doping regions and well pick-up regions during planarization, which results in inadequate performance and reduced production yield.
Innovation Solution
Incorporating a support structure on top of the first isolation structure to prevent over-polishing of the interlayer dielectric layer and protect the source/drain doping regions and well pick-up regions, thereby avoiding contact and contamination during the planarization process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If planarization process is performed to form interlayer dielectric layer, then flat surface is achieved, but top surface dishing occurs above first isolation structure
Solution Approach 1:
A support structure is formed on top of the first isolation structure before the planarization process. This support structure serves as a protective element that prevents over-polishing during planarization, thereby avoiding top surface dishing and maintaining the integrity of the underlying source/drain doping regions and well pick-up region.
Solution Approach 2:
The support structure acts as an intermediary element between the planarization tool and the sensitive regions (source/drain doping regions and well pick-up region). It absorbs the mechanical action of planarization, protecting the underlying structures from damage while still allowing the interlayer dielectric layer to be formed with adequate thickness.
2Shape
If planarization is performed to achieve flat surface, then interlayer dielectric layer can be formed, but source/drain doping regions and well pick-up region may be contacted or contaminated
Solution Approach 1:
The support structure is formed in advance on top of the first isolation structure, covering and protecting the source/drain doping regions and well pick-up region before the planarization process begins. This preliminary protective measure ensures that these sensitive regions are not exposed to the planarization tool, preventing contact and contamination.
Solution Approach 2:
The support structure serves as a protective intermediary that stands between the planarization tool and the sensitive source/drain doping regions and well pick-up region. It absorbs the mechanical action and prevents direct contact between the planarization tool and the underlying sensitive structures, thereby maintaining their integrity and preventing contamination.
3Shape
If interlayer dielectric layer thickness is reduced above first isolation structure, then planarization is improved, but performance of semiconductor structure deteriorates
Solution Approach 1:
The support structure is formed before the interlayer dielectric layer deposition and planarization processes. It provides a protective platform that allows the interlayer dielectric layer to maintain adequate thickness above the first isolation structure without compromising planarization quality, thereby preserving the performance and reliability of the semiconductor structure.
Solution Approach 2:
The support structure acts as a protective intermediary that enables the formation of the interlayer dielectric layer with sufficient thickness above the first isolation structure. It prevents over-polishing and maintains the mechanical integrity and electrical performance of the underlying source/drain doping regions and well pick-up region, ensuring overall device reliability.
Data Source
AI summary
Semiconductor structures and methods for forming same are disclosed. In one form, a structure includes: a base, including a first device region and a second device region, where the first device region includes a channel region, and preset regions located on two sides of the channel region, and a well pick-up region surrounding the channel region and the preset regions; a first isolation structure, located in the base between the preset regions and the well pick-up region and between the well pick-up region and the adjacent second device region; a poly gate, covering the channel region; a first source/drain doping region, located in the preset regions on two sides of the poly gate; a metal gate, located on the base in the second device region; a support structure, located on the top of the first isolation structure; and an interlayer dielectric layer, covering side walls of the poly gate, the metal gate, and the support structure. The support structure can mitigate a problem of top surface dishing of the interlayer dielectric layer above the first isolation structure, to avoid contacting the first source/drain doping region and the well pick-up region in a planarization process of forming the interlayer dielectric layer and the metal gate, thereby improving the performance of the semiconductor structure.