Semiconductor Structure With Isolation Layer Preventing Silicide Short-Circuit
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Solution Overview
Problem
Current semiconductor manufacturing technologies face challenges with short-circuiting between metal silicide layers in semiconductor devices, leading to malfunction due to the formation of vertices during epitaxial growth, which causes contact between different semiconductor devices.
Innovation Solution
The formation of an isolation layer with a surface higher than the vertices of the covering layers, limiting the growth directions of subsequent layers and preventing contact between them, ensuring electrical insulation between semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If metal silicide is formed to electrically connect drain and source regions, then device functionality is improved, but short-circuit between different devices occurs
Solution Approach 1:
The patent applies different material properties or structural characteristics to different regions of the covering layer. In regions where electrical connection is needed, the structure allows metal silicide formation, while in regions between adjacent devices, the structure is modified to prevent contact, creating local variations in electrical properties that satisfy both connectivity and isolation requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents short-circuiting between metal silicide layers, enhancing the reliability and functionality of semiconductor devices by maintaining electrical insulation and improving the integration degree of semiconductor devices.
Implementation Method 1
forming a first covering layer on a surface of the first stress layer and a second covering layer on a surface of the second stress layer by epitaxial growth
Data Source
AI summary
A fabrication method includes providing a base having a first transistor region and a second transistor region; forming a first stress layer in the first transistor region and a second stress layer in the second transistor region; forming a first covering layer on a surface of the first stress layer and a second covering layer on a surface of the second stress layer, with a gap between the first and the second covering layers exposing the surface of the base, and the neighboring side walls of the first and second covering layers have vertices pointing to each other; forming an isolation layer filling up the gap, and the isolation layer is higher than the vertices, exposing top surfaces of the first and second covering layers; and forming a third covering layer on the first covering layer and a fourth covering layer on the second covering layer.