Semiconductor Isolation Layers for Integration Density

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Solution Overview

Problem

The miniaturization of semiconductor devices requires effective electrical isolation between channels and substrates to enhance performance, which existing technologies have not adequately addressed.

Innovation Solution

A semiconductor device manufacturing method involving the formation of isolation layers by alternately stacking semiconductor layers, using sacrificial layers, and etching techniques to create fin-type structures and trenches, ensuring electrical isolation between the substrate and channel structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If semiconductor devices are miniaturized to increase integration density, then the distance between devices is reduced, but electrical isolation between channels and substrates becomes more difficult to achieve

Engineering Contradiction:
Improveintegration densityVSAvoidelectrical isolation
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The device structure is segmented into multiple distinct layers including first and second isolation layers, sacrificial layers, and alternating semiconductor layers. This segmentation allows each layer to perform specific functions - isolation layers provide electrical isolation while semiconductor layers form channels, enabling both high integration density and reliable electrical isolation even at reduced device distances

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the device structure are assigned different material properties and functions. Isolation layers use materials with specific dielectric properties to provide electrical isolation in critical regions, while semiconductor layers provide conductive channels. This local differentiation of material quality enables simultaneous achievement of miniaturization and electrical isolation

Inventive Principle:
Principle #3Local quality

2Reliability

If isolation layers are added to achieve electrical isolation, then device performance is improved, but manufacturing process complexity increases

Engineering Contradiction:
Improveelectrical isolationVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Sacrificial layers are formed preliminarily during the manufacturing process to define the positions and shapes of future isolation regions. These sacrificial layers are then selectively removed to create trenches, which are subsequently filled with isolation materials. This preliminary action approach simplifies the overall manufacturing process by establishing a clear sequence of operations

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Sacrificial layers serve as intermediary elements during manufacturing. They temporarily occupy the space where isolation trenches will eventually form, enabling precise trench formation through selective removal. This intermediary approach simplifies the manufacturing process by providing a controlled method to create complex isolation structures

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method effectively isolates the substrate from the channel, improving the performance and integration density of semiconductor devices, such as MBCFETs, by establishing reliable electrical isolation.

Implementation Method 1

partially etching the lowermost layer of the preliminary stack structure to form a second sacrificial layer pattern and to form a stack structure having a bottom surface at which one of the first preliminary semiconductor patterns is exposed

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS11557504B2Semiconductor device including isolation layers and method of manufacturing the same
Publication Date: 2023.01.17 SAMSUNG ELECTRONICS CO LTD
  • US11557504B2 patent drawing
  • US11557504B2 patent drawing
  • US11557504B2 patent drawing

AI summary

A semiconductor device includes: a pair of wire patterns configured to extend in a first direction and formed on a substrate to be spaced apart from each other in a second direction, the pair of wire patterns disposed closest to each other in the second direction; a gate electrode configured to extend in the second direction on the substrate, the gate electrode configured to surround the wire patterns; and first isolation layers configured to extend in the first direction between the substrate and the gate electrode and formed to be spaced apart from each other in the second direction, the first isolation layers overlapping the pair of wire patterns in a third direction perpendicular to the first and second directions.