Semiconductor structure and manufacturing method thereof
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Solution Overview
Problem
Large oxide diffusion areas in power devices experience increased crystal defects and current leakage due to manufacturing stresses, particularly in high or medium voltage applications.
Innovation Solution
The semiconductor structure incorporates a dielectric element embedded in the semiconductive substrate, laterally and vertically misaligned with doped regions, and isolation components spaced apart from the channel to reduce stress and prevent blockage, using shallow trench isolation (STI) techniques to form dielectric and isolation elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If large oxide diffusion area is used in power devices, then high voltage or medium voltage bearing capability is improved, but crystal defects and current leakage increase due to manufacturing stresses
Solution Approach 1:
The patent divides the large oxide diffusion area into multiple smaller diffusion regions by introducing isolation components (such as shallow trench isolation structures) between them. This segmentation reduces the continuous stress area, preventing crystal defects while maintaining the overall large diffusion area needed for high voltage bearing capability.
Solution Approach 2:
The patent introduces dielectric materials (isolation components) as intermediaries between the doped regions. These isolation components act as stress buffers that reduce manufacturing-induced stresses on the oxide diffusion areas, thereby preventing crystal defects and current leakage while allowing the large diffusion area to maintain its voltage bearing capability.
2Strength
If large oxide diffusion area is used in power devices, then high voltage or medium voltage bearing capability is improved, but crystal defects increase due to manufacturing stresses
Solution Approach 1:
The patent segments the large oxide diffusion area into smaller regions using isolation components, which reduces the stress concentration in each individual region. This segmentation approach maintains the overall large diffusion area for voltage bearing while improving manufacturing precision by reducing crystal defects in each segmented region.
Solution Approach 2:
The dielectric isolation components serve as intermediary structures that buffer manufacturing stresses. By placing these intermediaries between doped regions, the patent protects the oxide diffusion areas from stress-induced crystal defects, thereby improving manufacturing precision without compromising the voltage bearing capability.
3Productivity
If isolation components are placed close to the channel, then device performance is improved, but channel blockage occurs
Solution Approach 1:
The patent applies local quality by differentiating the spatial relationship between isolation components and the channel. The isolation components are positioned with specific spacing from the channel region, creating a local quality distinction where the channel area remains free of blockages while other areas benefit from the isolation structures for improved device performance.
Data Source
AI summary
The present disclosure provides a semiconductor structure, including a transistor. The transistor includes a semiconductive substrate, a gate structure, a pair of highly doped regions and a dielectric element. The semiconductive substrate has a top surface. The gate structure is over the top surface. The pair of highly doped regions is separated by the gate structure. The dielectric element is embedded in the semiconductive substrate. The dielectric element is laterally and vertically misaligned with the pair of highly doped regions.