Semiconductor Isolation Structures for Low-Leakage FinFET Gates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The complexity of semiconductor manufacturing processes increases with the scaling down of semiconductor devices, leading to challenges in maintaining strain in channel regions and degrading channel mobility performance, while existing isolation structures often result in high reverse-bias leakage currents and increased manufacturing costs.
Innovation Solution
The use of polysilicon gate structures with reverse bias configuration to provide electrical isolation between FET devices, achieving higher threshold voltages and smaller reverse-bias leakage currents without the need for complex work function metal deposition, thereby maintaining strain and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional isolation structures are used to electrically isolate FET devices, then electrical isolation is achieved, but reverse-bias leakage currents increase and manufacturing costs increase
Solution Approach 1:
The patent changes the electrical parameters of the fin structure by applying reverse bias voltage to create a depletion region that extends into the channel, thereby reducing reverse-bias leakage currents while maintaining electrical isolation between adjacent FET devices
Solution Approach 2:
The fin structure itself acts as an intermediary element that provides electrical isolation through reverse bias configuration, eliminating the need for additional isolation structures and reducing leakage currents without increasing manufacturing complexity
2Productivity
If scaling down of semiconductor devices is continued to increase storage capacity and processing speed, then device density and performance improve, but manufacturing process complexity increases and strain maintenance in channel regions becomes difficult
Solution Approach 1:
The fin structure serves multiple functions simultaneously: it provides mechanical strain for channel mobility enhancement, electrical isolation between devices through reverse bias, and defines the active channel region, thereby simplifying the overall manufacturing process while maintaining device performance at scaled dimensions
Solution Approach 2:
By changing the electrical bias parameters of the fin structure, the patent achieves multiple objectives including strain maintenance, electrical isolation, and leakage current reduction without requiring additional manufacturing steps, thus managing complexity during device scaling
3Reliability
If polysilicon gate structures with reverse bias configuration are used for electrical isolation, then threshold voltages increase and reverse-bias leakage currents decrease, but manufacturing complexity may increase
Solution Approach 1:
The existing fin structure serves as the intermediary element for electrical isolation, eliminating the need for separate polysilicon gate structures. The reverse bias applied to the fin structure itself achieves threshold voltage control and leakage current reduction without adding manufacturing complexity
Solution Approach 2:
The fin structure is designed to perform multiple functions including channel formation, strain provision, and electrical isolation through reverse bias configuration, thereby achieving threshold voltage control without requiring additional polysilicon gate structures or increasing manufacturing complexity
Data Source
AI summary
The structure of a semiconductor device with isolation structures between FET devices and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure on a substrate and forming polysilicon gate structures with a first threshold voltage on first fin portions of the fin structure. The method further includes forming doped fin regions with dopants of a first type conductivity on second fin portions of the fin structure, doping at least one of the polysilicon gate structures with dopants of a second type conductivity to adjust the first threshold voltage to a greater second threshold voltage, and replacing at least two of the polysilicon gate structures adjacent to the at least one of the polysilicon gate structures with metal gate structures having a third threshold voltage less than the first and second threshold voltages.