Semiconductor Isolation Structure for Residual Metal Removal
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving reliable isolation structures for transistors, particularly in the removal of metal layers during manufacturing, which can lead to defects such as bridge failures due to residual metal residues in recessed portions.
Innovation Solution
The semiconductor device incorporates isolation structures with a nitride liner that protrudes from the inner wall oxide and filling insulation patterns, creating recessed portions with increased widths, allowing for easy removal of metal layers and reducing defects by ensuring sufficient space for etching gases to flow and completely remove the metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional isolation structures are used to separate NMOS and PMOS transistors, then transistor isolation is achieved, but residual metal layers remain in recessed portions causing bridge failures
Solution Approach 1:
The isolation structure is segmented into multiple functional layers: inner wall oxide pattern for trench isolation, liner layer for structural integrity, and filling insulation pattern for complete recessed portion filling. This segmentation allows each layer to address specific issues, ensuring no residual metal layers remain in recessed portions while maintaining effective transistor isolation.
Solution Approach 2:
The invention extends the isolation structure vertically by having the liner and filling insulation pattern protrude from the upper surface of the substrate. This dimensional extension ensures that recessed portions are completely filled and capped, preventing bridge failures caused by residual metal layers while maintaining effective electrical isolation between transistors.
2Ease of manufacture
If standard gate structures are used for both NMOS and PMOS transistors, then manufacturing simplicity is maintained, but PMOS transistor performance and mobility are insufficient
Solution Approach 1:
Different gate structures are applied to different transistor regions: the first gate structure with P-type metal pattern is used for PMOS transistors to enhance mobility and control threshold voltage, while the second gate structure without P-type metal is used for NMOS transistors. This local differentiation optimizes performance for each transistor type while maintaining manufacturing feasibility through selective formation processes.
Data Source
AI summary
A semiconductor device includes first and second trenches in respective first and second regions in a substrate, a first isolation structure having a first inner wall oxide pattern, a first liner, and a first filling insulation pattern sequentially stacked I the first trench, a second isolation structure having a second inner wall oxide pattern, a second liner, and a second filling insulation pattern sequentially stacked I the second trench, a first gate structure having a first high-k dielectric pattern, a first P-type metal pattern, and a first N-type metal pattern sequentially stacked on the first region, and a second gate structure having a second high-k dielectric pattern and a second N-type metal pattern sequentially stacked on the second region, wherein the first and second liners protrude above upper surfaces of the first and second inner wall oxide patterns and the first and second filling insulation patterns, respectively.