Semiconductor Isolation Structure for Scaled MOSFET Reliability
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Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improvements in electrical and reliability characteristics.
Innovation Solution
The semiconductor device incorporates an active pattern defined by a trench on a substrate, filled with a device isolation layer, and features a gate electrode crossing the active pattern. Additionally, a first division structure is spaced apart from the gate electrode and extends in a direction perpendicular to the gate, with a power delivery network layer on the substrate's surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to meet increasing demand for smaller pattern size, then device size is reduced, but operational properties deteriorate
Solution Approach 1:
The device isolation layer is divided into a first isolation region and a second isolation region with different dielectric constants. This segmentation allows each region to serve different functional purposes: the first region provides standard isolation while the second region with higher dielectric constant improves electrical characteristics and reduces leakage current, thereby maintaining reliability despite device scaling.
Solution Approach 2:
Different regions of the device isolation layer are assigned different dielectric properties. The second isolation region positioned adjacent to the transistor channel uses a dielectric material with higher dielectric constant than the first isolation region, creating local quality variations that enhance electrical performance specifically where needed without affecting overall device size.
2Ease of manufacture
If device isolation layer uses uniform dielectric material, then manufacturing is simplified, but electrical characteristics deteriorate due to leakage current
Solution Approach 1:
The device isolation layer incorporates regions with different dielectric constants - a first isolation region with standard dielectric material and a second isolation region adjacent to the channel with higher dielectric constant material. This local differentiation reduces leakage current and improves electrical characteristics while maintaining reasonable manufacturing complexity through selective area processing.
Solution Approach 2:
The device isolation layer is constructed as a composite structure combining two different dielectric materials with different dielectric constants. This composite approach allows optimization of electrical performance by placing high-k material strategically near the channel while using standard materials in other regions, balancing electrical characteristics with manufacturing considerations.
Data Source
AI summary
A semiconductor device may include an active pattern on a substrate, defined by a trench, and extending in a first direction, a device isolation layer filling the trench, the substrate including a first surface in contact with a bottom surface of the device isolation layer and a second surface opposite to the first surface, a gate electrode extending in a second direction and cross the active pattern, the second direction crossing the first direction, a first division structure spaced apart from the gate electrode in the first and extending in the second direction, and a power delivery network layer on the second surface of the substrate. The first division structure may penetrate the device isolation layer, and a bottom surface of the first division structure may be coplanar with the second surface of the substrate.