Semiconductor Isolation Oxide Sequence for Short-Circuit Prevention

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Solution Overview

Problem

The shrinkage of active area pitch and isolation structure size in semiconductor devices leads to short circuit issues due to the deposition of rough silicon, which is not effectively addressed by existing manufacturing methods.

Innovation Solution

A manufacturing method involving the formation of a thin silicon layer followed by a first oxide layer at 400°C to 600°C, a second oxide layer using a cyclic process with oxygen and hydrogen, and an anneal process to crystalize the thin silicon layer, enlarging the active area and reducing short circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the pitch of active areas and isolation structure size are reduced to achieve higher integration, then device integration is improved, but short circuit issues occur due to rough silicon deposition

Engineering Contradiction:
Improvedevice integrationVSAvoidshort circuit prevention
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

A thin silicon layer is formed on the active area and trench sidewall before the isolation structure formation, and this layer is subsequently crystalized through annealing to prevent rough silicon deposition that would cause short circuits

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the physical state of the thin silicon layer from amorphous to crystalline through thermal annealing at specific temperature ranges, which fundamentally alters its properties to prevent harmful rough silicon deposition

Inventive Principle:
Principle #35Parameter changes

2Reliability

If a thin silicon layer is formed and crystalized to prevent rough silicon deposition, then short circuit prevention is improved, but the process complexity increases

Engineering Contradiction:
Improveshort circuit preventionVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The formation of the thin silicon layer and its subsequent crystalization through annealing is integrated into the existing semiconductor manufacturing process flow, combining multiple functions into a unified process sequence that includes hard mask formation, trench etching, thin silicon deposition, and thermal annealing

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method increases the active area size while minimizing short circuits by forming a stable oxide layer to prevent rough silicon deposition, thus enhancing semiconductor device integrity.

Implementation Method 1

A first oxide layer is formed on the thin silicon layer by providing oxygen airflow, wherein the first oxide layer is formed in a range of 400°C to 600°C

Methodology Applied
Scientific EffectOxidation: Oxidation

Implementation Method 2

an anneal process is performed to crystalize the thin silicon layer

Methodology Applied
Scientific EffectAnnealing: Annealing

Implementation Method 3

an anneal process is performed to crystalize the thin silicon layer

Methodology Applied
Scientific EffectCrystallization: Crystallisation

Data Source

PatentUS20260005016A1Manufacturing method of semiconductor structure
Publication Date: 2026.01.01 NAN YA TECH
  • US20260005016A1 patent drawing
  • US20260005016A1 patent drawing
  • US20260005016A1 patent drawing

AI summary

A manufacturing method of a semiconductor structure is provided. The method includes following steps. A substrate is provided. A trench is formed in the substrate, wherein an active area is protruded from the substrate and the active has a first width. A thin silicon layer is formed on the active area and a sidewall of the trench. A first oxide layer is formed on the thin silicon layer by providing oxygen airflow, wherein the first oxide layer is formed in a range of 400°C to 600°C. A second oxide layer is formed to fill the trench and cover the active area, wherein the second oxide layer is formed at a temperature higher than the first oxide layer. And an anneal process is performed to crystalize the thin silicon layer.