Semiconductor Isolation Structure for Planar Trench Filling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The issue of material filling and planar results in semiconductor manufacturing leads to unwanted residue and defects, increasing manufacturing costs and reducing product yield due to uneven surfaces and incomplete metal gate replacements.
Innovation Solution
A method is introduced to integrate the formation of different isolations, providing a common planar surface by forming trenches and filling them with layers, followed by precise etching operations to achieve a semiconductor structure with varying trench isolations and a planar top surface, ensuring complete metal gate replacement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If material filling is performed in conventional semiconductor manufacturing, then device density is increased, but unwanted residue and defects are generated due to uneven surfaces
Solution Approach 1:
The patent segments the isolation formation process into multiple distinct steps: forming first and second trenches at different locations, filling them with different dielectric materials, and performing selective planarization. This segmentation allows each trench to be optimized independently, eliminating the residue problems that occur when attempting to fill all trenches uniformly in conventional processes.
Solution Approach 2:
The patent introduces a vertical dimension to the isolation structure by creating trenches at different depths and filling them with different materials. The first trench extends to a first depth while the second trench extends to a second depth, creating a multi-level isolation architecture that enables complete material removal and replacement without residue.
2Ease of manufacture
If conventional isolation formation methods are used, then manufacturing process is simpler, but incomplete metal gate replacement occurs due to uneven trench surfaces
Solution Approach 1:
The patent performs preliminary planarization of each trench surface before metal gate formation. The first trench surface is planarized to a first level and the second trench surface is planarized to a second level, ensuring that when metal gates are subsequently formed, they can be completely replaced without residue from previous materials. This preliminary action prevents the reliability issues of incomplete replacement.
Solution Approach 2:
The patent applies different isolation materials and planarization levels to different local regions (trenches) based on their specific requirements. Each trench receives tailored treatment with appropriate dielectric material and planarization depth, ensuring optimal conditions for complete metal gate replacement in each location while maintaining overall process feasibility.
3Manufacturing precision
If multiple isolations are formed separately, then each isolation can be optimized, but manufacturing cost increases and productivity decreases
Solution Approach 1:
The patent merges multiple isolation formation operations into a single integrated process flow. Multiple trenches are formed and filled in one sequence, with planarization steps that address all trenches simultaneously or in an optimized sequence. This merging maintains the optimization benefits of separate isolation formation while improving manufacturing efficiency by eliminating redundant process steps.
Data Source
AI summary
A semiconductor structure includes a first, second and third isolations. The first isolation and a second isolation are disposed in a substrate and substantially parallel to each other, wherein a portion of the substrate is disposed between the first isolation and the second isolations. The third isolation is disposed over the portion of the substrate between the first and second isolations. A top surface of the third isolation is substantially aligned with top surfaces of the first and second isolations. A first step is between a bottom surface of the third isolation and a bottom surface of the first isolation. A second step between the bottom surface of the third isolation and a bottom surface of the second isolation. A method for manufacturing a semiconductor structure is also provided.